Simulink HDL Coder & Vitis Model Composer cannot find the same Device

I have the error pictured below when attempting to generate VHDL code through the HDL code generator in Simulink. Both the Devices match to the best of my knowledge ... My only idea is that it is for some reason due to using Vitis Model Composer 2022.2 and Matlab R2022a. However, I don't think this would be the case as well because I could generate code when I had no Xilinx block and the same versions of software mentioned before.

Answer 1

[Kiran Kintali]

Model Composer library in Simulink needs Vitis workflows to generate HDL Code.

https://www.xilinx.com/products/design-tools/vitis/vitis-model-composer.html

Are you trying to use Model Composer blocks in a subsystem and using HDL Coder to generate code from them?

Can you share a sample model or some more details on what your DUT (device under test) subsystem contains when using HDL Coder or HDL Workflow Advisor?

Thanks

[denkvakva]

I updated the question to include the generic example I created

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

Using Xilinx System Generator for DSP with HDL Coder

This feature is not yet made compatible with Model Composer blocks. This is on the development team roadmap. I have reported this to the development team.

[denkvakva]

I have now gotten them to work together by treating the xilinx system as a black box in the HDL block properties.

Once you do that then you can generate HDL code through the "Vitis Model Composer" for your specific "Black Box".

Then generate HDL code like normal for the entire system...

Then you must manually conbine them in the Vivado project by adding then black boxes as Design Sources

You do have to get the variables to line up in either vivado or in the HDL properties before the HDL Code Generator runs, Match them to the HDL code created from the "Vitis Model Composer"

[Kiran Kintali]

That's looks like a resonable approach. Thanks for sharing it.

Here are few steps to summarize the workaround.

1. Create a Simulink model with a Simulink DUT with built-in blocks and a subsystem containg XMC blocks
2. Mark XMC subsystem as a HDL Blackbox interface
3. Generate HDL Code for the DUT with HDL Coder
4. Generate HDL Code for the XMC subsystem with Vitis Model Composer
5. Manually combine the generated code from step3 and step4.
6. Build the code with Vivado Synthesis tool