why do i get this error?
2 views (last 30 days)
Show older comments
PARVATHY NAIR on 10 Jan 2023
Commented: Kiran Kintali on 11 Jan 2023
why am i getting this error while changing matlab code to hdl code
Kiran Kintali on 10 Jan 2023
Can you share the design, testbench and the project files?
It looks like you are running into some issue with classes during floating point to fixed point conversion.
Edited: Kiran Kintali on 11 Jan 2023
Please attach files that can run without error. I got an error running the runtrial.m file.
You need break the design that needs to be on the FPGA in a seperate file. There is plotting and figure window related code in ada.m that needs to move into the testbench.
This file is missing BKHL.HHE.new.dat in your attachments.
Changing this to the attached csv file name leads to other errors.
Unable to perform assignment because the size of the
left side is 1-by-1 and the size of the right side is
Error in ada (line 76)
err_VSS(itr,:) = error.^2;
Error in runtrial (line 4)
Find more on MATLAB Cosimulation in Help Center and File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!Start Hunting!