HDL FIFO accepts three more pushes before signalling full

I'm trying to understand the operation of the HDL FIFO. See an image of my test system below.

It has a register size of 5 in FWFT mode. The push_signal is [0 0 0 1 0 0 0 1 ....], that is, true every 4th sample. I use this because it seems there's a 3-cycle latency before the FIFO empty signal drops. I guess this is imitating the hardware behavior. (Actually the 3 cycles only happens at the start - when it goes empty later, there's only 1 cycle of latency)

The strange thing happens when I gate the push signal on the not_full signal. "Full" is not asserted until there are 8 pushes (1 cycle after). But it's supposed to only hold 5 elements!

The pop_signal is the same as push_signal except delayed by 36 samples. When I pop until empty is asserted, I get back all eight elements that were pushed. It's as if the block added 3 to my register size. Seems to happen no matter how big I make the FIFO. What am I doing wrong?

Thanks for any help

Charles

Signal graph below; I hope it's readable.

Answer 1

[Kiran Kintali]

Can you share the model? thanks

[Charles]

Sure - see attached

Edit: added the loadVar script called from the initFcn callback.

[Kiran Kintali]

FWFT mode seems to have few extra registers that can hold up to three values past the specified size of the RAM/FIFO. I have created a task to update the documentation.

Please reach out to tech support for additional help or requirements on this topic.

[Charles]

Thanks for looking at this. I was still left wondering why this was the behavior, and it turns out it's more or less because that's the way FPGA companies do it. Here is the best link I found: First-Word Fall-Through (FWFT) Read Operation. There's even a reference to the extra latency cycles for the first element. At any rate, I hope the updated documentation includes this kind of nuance.