HDL FIFO accepts three more pushes before signalling full
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Commented: Charles on 5 Dec 2022
I'm trying to understand the operation of the HDL FIFO. See an image of my test system below.
It has a register size of 5 in FWFT mode. The push_signal is [0 0 0 1 0 0 0 1 ....], that is, true every 4th sample. I use this because it seems there's a 3-cycle latency before the FIFO empty signal drops. I guess this is imitating the hardware behavior. (Actually the 3 cycles only happens at the start - when it goes empty later, there's only 1 cycle of latency)
The strange thing happens when I gate the push signal on the not_full signal. "Full" is not asserted until there are 8 pushes (1 cycle after). But it's supposed to only hold 5 elements!
The pop_signal is the same as push_signal except delayed by 36 samples. When I pop until empty is asserted, I get back all eight elements that were pushed. It's as if the block added 3 to my register size. Seems to happen no matter how big I make the FIFO. What am I doing wrong?
Thanks for any help
Signal graph below; I hope it's readable.
Kiran Kintali on 5 Dec 2022
Can you share the model? thanks
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