HDL Coder fails to generate VHDL, Assertion failed: b:\matlab\​src\cgir_h​dl\pir_tra​nsforms\co​recomplowe​ring.hpp:9​7

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I have an HDL Coder Simulink model in R2020b. I use a script to run the HDL Coder workflow which works fine until I started seeing this cryptic error.
Error using hdlcoder.pirctx/createCGIR
Assertion failed:
b:\matlab\src\cgir_hdl\pir_transforms\corecomplowering.hpp:97:<Component CtxName="hw_tb" RefNum="c57" UserName="Selector" RTTIClass ="class pir::SelectorComp"
Network="n451"/>
Error in slhdlcoder.HDLCoder/runGenerateCGIR
Error in slhdlcoder.HDLCoder/makehdl
Error in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbench
Error in hwcli.runWorkflow
Error in hdlcoder.runWorkflow (line 27)
hwcli.runWorkflow( varargin{:} );
Error in generate_hdl (line 350)
hdlcoder.runWorkflow(hdl_sys, hWC);
I'm lost on what the issue could be. Does anyone have any tips on what could be going on here? What does CGIR, or PIR mean?

Accepted Answer

Ryan
Ryan on 28 Nov 2022
I solved my own problem. This error came from a Selector block configured to use the index from a port, and whose input was a vector of bus type signals. My intent was to use the Selector as a mux to choose only 1 element from a vector of bus signals. To work around this error, I broke apart the bus vector within a for-each subsystem and bit concatenated all bus elements into a set of uint32 signals. Then, I muxed the vector of uint32 type signals instead of the busses.

More Answers (1)

Kiran Kintali
Kiran Kintali on 29 Nov 2022
This is an unexpected error. Can you file a bug report with the support team? There should be a readable error message in case of unsupported modeling construct used in Simulink or HDL code generated from the model. Thanks.

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R2020b

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