Synthesis keeps on running for indefinite time on Xilinx RFSOC ZCU111

I tried to validate the example "5G NR MIB recovery using Xilinx RFSOC ZCU111" and able to complete the steps before synthesis (i.e., the step-7). Once I started the synthesis operation, it keeps on running for indefinite time.

The vesrions of Vivado and MATLAb are 2020.1 and 2021b, respectively, which is as per the the following accepted answer: https://in.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-coder#answer_426424

I will appreciate if someone can help on the same.

[John O'Sullivan]

Hi Abhay

When you start the sythesis step are you seeing the external shell window pop up? This should display the output from Vivado and may provide some indication of what is happening.

A Vivado project is created by the SoC Builder workflow. You can also try opening this project directly in Vivado, and running synthesis from there to see if this provides some insight into the problem.

Thanks,

John

[John O'Sullivan]

I tried running synthesis using the same versions mentioned (MATLAB 21b and Vivado 20.1). I was able to generate a bitstream. It took around 2.5-3 hours from the Vivado external shell opening to generate a bitstream (synthesis + implementation + bitstream generation). I did notice that the external shell seemed to be stuck at some points, but pushing the return key seemed to get it to update with the latest output from the Vivado log.

Answer 1

[Kiran Kintali]

Please reach out to support if you still run into this issue.