# N-Channel MOSFET

N-Channel metal oxide semiconductor field effect transistor using either Shichman-Hodges equation or surface-potential-based model

**Libraries:**

Simscape /
Electrical /
Semiconductors & Converters

## Description

The N-Channel MOSFET block provides two main modeling options:

Based on threshold voltage — Uses the Shichman-Hodges equation to represent the device. This modeling approach, based on threshold voltage, has the benefits of simple parameterization and simple current-voltage expressions. However, these models have difficulty in accurately capturing transitions across the threshold voltage and lack some important effects, such as velocity saturation. For details, see Threshold-Based Model.

This modeling option provides four ways of parameterizing an N-Channel MOSFET:

By specifying parameters from a datasheet.

By specifying equation parameters directly.

By a 2-D lookup table approximation to the I-V (current-voltage) curve. For details, see Representation by 2-D Lookup Table.

By a 3-D lookup table approximation to the I-V (current-voltage) curve that includes temperature data. For details, see Representation by 3-D Lookup Table.

Based on surface potential — Uses the surface-potential equation to represent the device. This modeling approach provides a greater level of model fidelity than the simple square-law (threshold-voltage-based) models can provide. The trade-off is that there are more parameters that require extraction. For details, see Surface-Potential-Based Model.

Together with the thermal port options (see Thermal Port), the block therefore provides you with four choices. To select the desired option, set the
**Modeling option** parameter to either:

**Threshold-based**— Basic model, which represents the device using the Shichman-Hodges equation (based on threshold voltage) and does not simulate thermal effects. This is the default.**Threshold-based with thermal**— Model based on threshold voltage and with exposed thermal port.**Surface-potential-based**— Model based on surface potential. This model does not simulate thermal effects.**Surface-potential-based with thermal**— Thermal modeling option of the model based on surface potential.

### Threshold-Based Model

The threshold-based option of the block uses the Shichman and Hodges equations [1] for an insulated-gate field-effect transistor to represent an N-Channel MOSFET.

The drain-source current, *I _{DS}*, depends on the
region of operation:

In the off region (

*V*<_{GS}*V*), the drain-source current is:_{th}$${I}_{DS}=0$$

In the linear region (0 <

*V*<_{DS}*V*–_{GS}*V*), the drain-source current is:_{th}$${I}_{DS}=K\left(({V}_{GS}-{V}_{th}){V}_{DS}-{V}_{DS}{}^{2}/2\right)\left(1+\lambda \left|{V}_{DS}\right|\right)$$

In the saturated region (0 <

*V*–_{GS}*V*<_{th}*V*), the drain-source current is:_{DS}$${I}_{DS}=(K/2){({V}_{GS}-{V}_{th})}^{2}\left(1+\lambda \left|{V}_{DS}\right|\right)$$

In the preceding equations:

*K*is the transistor gain.*V*is the positive drain-source voltage._{DS}*V*is the gate-source voltage._{GS}*V*is the threshold voltage. For the four terminal parameterization,_{th}*V*is obtained using these equations:_{th}*V*Range_{BS}*V*Equation_{th}$${V}_{BS}\le 0$$ $${V}_{th}={V}_{T0}+\gamma \left(-\sqrt{2{\varphi}_{B}}\right)+\gamma \left(\sqrt{2{\varphi}_{B}-{V}_{BS}}\right)$$ $$0<{V}_{BS}\le 4{\varphi}_{B}$$ $${V}_{th}={V}_{T0}-\frac{\gamma {V}_{BS}}{\sqrt{2{\varphi}_{B}}}$$ $${V}_{BS}>4{\varphi}_{B}$$ $${V}_{th}={V}_{T0}+\gamma \left(-\sqrt{2{\varphi}_{B}}\right)$$ *λ*is the channel modulation.

### Charge Model for Threshold-Based Modeling Option

The block models capacitances either by fixed capacitance values, or by tabulated values as
a function of the drain-source voltage. In either case, you can either directly specify the
gate-source and gate-drain capacitance values, or let the block derive them from the input
and reverse transfer capacitance values. Therefore, the
**Parameterization** options for charge model on the
**Capacitance** setting are:

`Specify fixed input, reverse transfer and output capacitance`

— Provide fixed parameter values from datasheet and let the block convert the input and reverse transfer capacitance values to capacitance values, as described below. This is the default method.`Specify fixed gate-source, gate-drain and drain-source capacitance`

— Provide fixed values for capacitance parameters directly.`Specify tabulated input, reverse transfer and output capacitance`

— Provide tabulated capacitance and drain-source voltage values based on datasheet plots. The block converts the input and reverse transfer capacitance values to capacitance values, as described below.`Specify tabulated gate-source, gate-drain and drain-source capacitance`

— Provide tabulated values for capacitances and drain-source voltage.

Use one of the tabulated capacitance options (```
Specify tabulated input, reverse
transfer and output capacitance
```

or ```
Specify tabulated
gate-source, gate-drain and drain-source capacitance
```

) when the datasheet
provides a plot of capacitances as a function of drain-source voltage. Using tabulated
capacitance values gives more accurate dynamic characteristics and avoids the need for
interactive tuning of parameters to fit the dynamics.

If you use the ```
Specify fixed gate-source, gate-drain and drain-source
capacitance
```

or ```
Specify tabulated gate-source, gate-drain and
drain-source capacitance
```

option, the **Capacitance**
setting lets you specify the **Gate-drain capacitance, Cgd**,
**Gate-source capacitance, Cgs**, and **Drain-source capacitance,
Cds** parameter values (fixed or tabulated) directly. Otherwise, the block
derives them from the **Input capacitance, Ciss**, **Reverse
transfer capacitance, Crss**, and **Output capacitance, Coss**
parameter values. These two parameterization methods are related as follows:

*C*=_{GD}*Crss**C*=_{GS}*Ciss*–*Crss**C*=_{DS}*Coss*–*Crss*

For the four terminals parameterization, the **Input capacitance, Ciss**,
**Reverse transfer capacitance, Crss**, and **Output capacitance,
Coss** are obtained using these equations:

*C*=_{GD}*Crss**C*+_{GS}*C*=_{GB}*Ciss*–*Crss**C*=_{DB}*Coss*–*Crss*

A simplified Meyer's capacitance model is used to describe the gate-source capacitance,
*C _{GS}*, the gate-bulk capacitance,

*C*, and the gate-drain capacitance,

_{GB}*C*. These figures show how the gate-bulk and gate-source capacitances change instantaneously, while the

_{GD}Gate-bulk and gate-source capacitance change instantaneously.

The two fixed capacitance options (```
Specify fixed input, reverse transfer and
output capacitance
```

or ```
Specify fixed gate-source, gate-drain and
drain-source capacitance
```

) let you model gate capacitance as a fixed
gate-source capacitance *C _{GS}* and either a fixed or
a nonlinear gate-drain capacitance

*C*. If you select the

_{GD}`Gate-drain charge function is nonlinear`

option for the
**Gate-drain charge-voltage linearity**parameter, then the gate-drain charge relationship is defined by the piecewise-linear function shown in the following figure.

For instructions on how to map a time response to device capacitance values, see the N-Channel IGBT block reference page. However, this mapping is only approximate because the Miller voltage typically varies more from the threshold voltage than in the case for the IGBT.

**Note**

Because this block implementation includes a charge model, you must model the impedance of the circuit driving the gate to obtain representative turn-on and turn-off dynamics. Therefore, if you are simplifying the gate drive circuit by representing it as a controlled voltage source, you must include a suitable series resistor between the voltage source and the gate.

### Representation by 2-D Lookup Table

For the lookup table representation of the detailed block modeling option, you provide tabulated values for drain-source currents as a function of gate-source voltage and drain-source voltage. The main advantage of using this option is simulation speed. It also lets you parameterize the device from either measured data or from data obtained from another simulation environment.

This figure shows the implementation of the 2-D lookup table option when you set
**Ids-Vds parameterization** to ```
Provide negative and positive Vds
data
```

:

This figure shows the implementation of the 2-D lookup table option when you set
**Ids-Vds parameterization** to ```
Provide positive Vds data
only
```

:

For the four terminal MOSFET, the surface potential and body factor values are calculated based on the nearest threshold voltage as shown in this picture:

**Note**

To ensure that the signs of the drain-source current and drain-source voltage are consistent:

If the drain-source voltage is equal to

`0`

, the value of the**Tabulated drain-source currents, Ids(Vgs,Vds)**parameter must be equal to`0`

.The tabulated power, which is the product of the

**Tabulated drain-source currents, Ids(Vgs,Vds)**parameter and the drain-source voltage, must be greater than or equal to`0`

.The tabulated conductance, which is the gradient of the

**Tabulated drain-source currents, Ids(Vgs,Vds)**parameter with respect to the drain-source voltage*V*, must be greater than or equal to_{ds}`0`

.The first gradient of the

**Tabulated drain-source currents, Ids(Vgs,Vds)**parameter, with respect to gate-source voltage*V*, must be equal to_{gs}`0`

.

### Representation by 3-D Lookup Table

For the temperature-dependent lookup table representation of the detailed block modeling option, you provide tabulated values for drain-source currents as a function of gate-source voltage, drain-source voltage, and temperature.

**Note**

To ensure that the signs of the drain-source current and drain-source voltage are consistent:

If the drain-source voltage is equal to

`0`

, the value of the**Tabulated drain-source currents, Ids(Vgs,Vds,T)**parameter must be equal to`0`

.The tabulated power, which is the product of the

**Tabulated drain-source currents, Ids(Vgs,Vds,T)**parameter and the drain-source voltage, must be greater than or equal to`0`

.The tabulated conductance, which is the gradient of the

**Tabulated drain-source currents, Ids(Vgs,Vds,T)**parameter with respect to the drain-source voltage*V*, must be greater than or equal to_{ds}`0`

.The first gradient of the

**Tabulated drain-source currents, Ids(Vgs,Vds,T)**parameter, with respect to gate-source voltage*V*, must be equal to_{gs}`0`

.

### Surface-Potential-Based Model

The surface-potential-based modeling option of the block provides a greater level of model fidelity than the simple square-law (threshold-voltage-based) model. The surface-potential-based block modeling option includes the following effects:

Fully nonlinear capacitance model (including the nonlinear Miller capacitance)

Charge conservation inside the model, so you can use the model for charge sensitive simulations

Velocity saturation and channel-length modulation

The intrinsic body diode

Reverse recovery in the body diode model

Temperature scaling of physical parameters

For the thermal modeling option, dynamic self-heating (that is, you can simulate the effect of self-heating on the electrical characteristics of the device)

This model is a minimal version of the world-standard PSP model (see https://briefs.techconnect.org/papers/introduction-to-psp-mosfet-model/), including only certain effects from the PSP model in order to strike a balance between model fidelity and complexity. For details of the physical background to the phenomena included in this model, see [2].

The basis of the model is Poisson equation:

$$\frac{{\partial}^{2}\psi}{\partial {x}^{2}}+\frac{{\partial}^{2}\psi}{\partial {y}^{2}}=\frac{q{N}_{A}}{{\epsilon}_{Si}}\left[1-\mathrm{exp}\left(\frac{-\psi}{{\varphi}_{T}}\right)+\mathrm{exp}\left(\frac{\psi -2{\varphi}_{B}-{V}_{CB}}{{\varphi}_{T}}\right)\right]$$

$${\varphi}_{T}=\frac{{k}_{B}T}{q}$$

where:

*ψ*is the electrostatic potential.*q*is the magnitude of the electronic charge.*N*is the density of acceptors in the substrate._{A}*ɛ*is the dielectric permittivity of the semiconductor material (for example, silicon)._{Si}*ϕ*is the difference between the intrinsic Fermi level and the Fermi level in the bulk silicon._{B}*V*is the quasi-Fermi potential of the surface layer referenced to the bulk._{CB}*ϕ*is the thermal voltage._{T}*k*is Boltzmann’s constant._{B}*T*is temperature.

Poisson equation is used to derive the surface-potential equation:

$${\left({V}_{GB}-{V}_{FB}-{\psi}_{s}\right)}^{2}={\gamma}^{2}\left[{\psi}_{s}+{\varphi}_{T}\left(\mathrm{exp}\left(\frac{-{\psi}_{s}}{{\varphi}_{T}}\right)-1\right)+{\varphi}_{T}\mathrm{exp}\left(-\frac{2{\varphi}_{B}+{V}_{CB}}{{\varphi}_{T}}\right)\left(\mathrm{exp}\left(\frac{{\psi}_{s}}{{\varphi}_{T}}\right)-1\right)\right]$$

where:

*V*is the applied gate-body voltage._{GB}*V*is the flatband voltage._{FB}*ψ*is the surface potential._{s}*γ*is the body factor,

$$\gamma =\frac{\sqrt{2q{\epsilon}_{Si}{N}_{A}}}{{C}_{ox}}$$

*C*is the capacitance per unit area._{ox}

The block uses an explicit approximation to the surface-potential equation, to avoid the need for numerical solution to this implicit equation.

Once the surface potential is known, the drain current
*I _{D}* is given by

$${I}_{D}=\frac{W{\mu}_{0}}{L{G}_{\Delta L}{G}_{mob}\sqrt{1+{\left({\theta}_{sat}\Delta \psi \right)}^{2}}}\left[-{\overline{Q}}_{inv}\Delta \psi +{\varphi}_{T}\left({Q}_{invL}-{Q}_{inv0}\right)\right]$$

where:

*W*is the device width.*L*is the channel length.*μ*is the low-field mobility._{0}*θ*is the velocity saturation._{sat}*Δψ*is the difference in the surface potential between the drain and the source.*Q*and_{inv0}*Q*are the inversion charge densities at the source and drain, respectively._{invL}$${\overline{Q}}_{inv}$$ is the average inversion charge density across the channel.

*G*is the mobility reduction factor. For more information, see the_{mob}**Surface roughness scattering factor**parameter description in the Main (Surface-Potential-Based Modeling Option) section.*G*is the channel-length modulation._{ΔL}

$${G}_{\Delta L}=1-\frac{\Delta L}{L}=1-\alpha \mathrm{ln}\left[\frac{{V}_{DB}-{V}_{DB,eff}+\sqrt{{\left({V}_{DB}-{V}_{DB,eff}\right)}^{2}+{V}_{p}^{2}}}{{V}_{p}}\right]$$

where:

*α*is the channel-length modulation factor.*V*is the drain-body voltage._{DB}*V*is the drain-body voltage clipped to a maximum value corresponding to velocity saturation or pinch-off (whichever occurs first)._{DB,eff}*V*is the channel-length modulation voltage._{p}

The block computes the inversion charge densities directly from the surface potential.

The block also computes the nonlinear capacitances from the surface potential. Source and drain charge contributions are assigned via a bias-dependent Ward-Dutton charge-partitioning scheme, as described in [3]. These charges are computed explicitly, so this model is charge-conserving. The capacitive currents are computed by taking the time derivatives of the relevant charges. In practice, the charges within the simulation are normalized to the oxide capacitance and computed in units of volts.

The MOSFET gain, β, is given by

$$\beta =\frac{W{\mu}_{0}{C}_{ox}}{L}$$

The threshold voltage for a short-circuited source-bulk connection is approximately given by

$${V}_{T}={V}_{FB}+2{\varphi}_{B}+2{\varphi}_{T}+\gamma \sqrt{2{\varphi}_{B}+2{\varphi}_{T}}$$

where:

2

*ϕ*is the surface potential at strong inversion._{B}

The overall three and four terminal models consist of an intrinsic MOSFET defined by the surface-potential formulation, a body diode, series resistances, and fixed overlap capacitances, as shown in the schematics.

### Modeling Body Diode

The block models the body diode either as an ideal, exponential diode or as a tabulated diode.

**Exponential Diode**

When you set **Model body diode** to
`Exponential`

, the junction and diffusion capacitances are:

$${I}_{dio}={I}_{s}\left[\mathrm{exp}\left(-\frac{{V}_{DB}}{n{\varphi}_{T}}\right)-1\right]$$

$${C}_{j}=\frac{{C}_{j0}}{\sqrt{1+\frac{{V}_{DB}}{{V}_{bi}}}}$$

$${C}_{diff}=\frac{\tau {I}_{s}}{n{\varphi}_{T}}\mathrm{exp}\left(-\frac{{V}_{DB}}{n{\varphi}_{T}}\right)$$

where:

*I*is the current through the diode._{dio}*I*is the reverse saturation current._{s}*V*is the drain-body voltage._{DB}*n*is the ideality factor.*ϕ*is the thermal voltage._{T}*C*is the junction capacitance of the diode._{j}*C*is the zero-bias junction capacitance._{j0}*V*is the built-in voltage._{bi}*C*is the diffusion capacitance of the diode._{diff}*τ*is the transit time.

The capacitances are defined through an explicit calculation of charges, which are then differentiated to give the capacitive expressions above. The block computes the capacitive diode currents as time derivatives of the relevant charges, similar to the computation in the surface-potential-based MOSFET model.

**Tabulated Diode**

To model a tabulated diode, set the **Model body diode** parameter to
`Tabulated I-V curve`

. This figure shows the implementation of the
tabulated diode option:

When choosing this parameterization, you must provide the data for the forward bias only.

The block implements the diode using a smooth interpolation option. If the diode exceeds the provided tabulated data range, the block uses a linear extrapolation technique at the last voltage-current data point.

**Note**

The tabulated diode does not model the reverse breakdown.

### Modeling Temperature Dependence

The default behavior is that dependence on temperature is not modeled, and the device is
simulated at the temperature for which you provide block parameters. To model the dependence on
temperature during simulation, select `Model temperature dependence`

for the **Parameterization** parameter in the **Temperature
Dependence** setting.

**Threshold-Based Model**

For threshold-based modeling option, you can include modeling the dependence of the transistor static behavior on temperature during simulation. Temperature dependence of the capacitances is not modeled, this being a much smaller effect.

When including temperature dependence, the transistor defining equations remain the same.
The gain, *K*, and the threshold voltage,
*V _{th}*, become a function of temperature according to
the following equations:

$${K}_{Ts}={K}_{Tm1}{\left(\frac{{T}_{s}}{{T}_{m1}}\right)}^{BEX}$$

*V _{ths}* =

*V*+

_{th1}*α*(

*T*–

_{s}*T*)

_{m1}where:

*T*is the temperature at which the transistor parameters are specified, as defined by the_{m1}**Measurement temperature**parameter value.*T*is the simulation temperature._{s}*K*is the transistor gain at the measurement temperature._{Tm1}*K*is the transistor gain at the simulation temperature. This is the transistor gain value used in the MOSFET equations when temperature dependence is modeled._{Ts}*V*is the threshold voltage at the measurement temperature._{th1}*V*is the threshold voltage at the simulation temperature. This is the threshold voltage value used in the MOSFET equations when temperature dependence is modeled._{ths}*BEX*is the mobility temperature exponent. A typical value of*BEX*is -1.5.*α*is the gate threshold voltage temperature coefficient,*d**V*/_{th}*d**T*.

For the four terminals parameterization, *V _{th}* is
obtained using these equations:

V Range_{BS} | V Equation_{th} |
---|---|

$${V}_{BS}\le 0$$ | $$\frac{d{V}_{th}}{dT}=\frac{d{V}_{T0}}{dT}-\frac{\gamma}{2\sqrt{2{\varphi}_{B}}}\frac{d2{\varphi}_{B}}{dT}+\frac{\gamma}{2\sqrt{2{\varphi}_{B}-{V}_{BS}}}\frac{d2{\varphi}_{B}}{dT}$$ |

$$0<{V}_{BS}\le 4{\varphi}_{B}$$ | $$\frac{d{V}_{th}}{dT}=\frac{d{V}_{T0}}{dT}-\frac{\gamma {V}_{BS}}{4}{\left(2{\varphi}_{B}\right)}^{-\frac{3}{2}}\frac{d2{\varphi}_{B}}{dT}$$ |

$${V}_{BS}>4{\varphi}_{B}$$ | $$\frac{d{V}_{th}}{dT}=\frac{d{V}_{T0}}{dT}-\frac{\gamma}{2\sqrt{2{\varphi}_{B}}}\frac{d2{\varphi}_{B}}{dT}$$ |

Where:

$${\varphi}_{B}=\frac{kT}{q}\mathrm{ln}\left(\frac{{N}_{B}}{{n}_{i}}\right)$$ is the surface potential and $$\frac{d2{\varphi}_{B}}{dT}=\frac{1}{T}\left[2{\varphi}_{B}-\left(\frac{{E}_{g}(0)}{q}+\frac{3kT}{q}\right)\right]$$.

*E*is the extrapolated zero degree band-gap, which is equal to_{g}(0)`1.16`

`eV`

for silicon.*V*is the bulk-source voltage._{BS}

For most MOSFETS, you can use the default value of `-1.5`

for
*BEX*. Some datasheets quote the value for *α*, but most
typically they provide the temperature dependence for drain-source on resistance,
*R _{DS}(on)*. Depending on the block parameterization
method, you have two ways of specifying

*α*:

If you parameterize the block from a datasheet, you have to provide

*R*at a second measurement temperature. The block then calculates the value for_{DS}(on)*α*based on this data.If you parameterize by specifying equation parameters, you have to provide the value for

*α*directly.

If you have more data comprising drain current as a function of gate-source voltage for
more than one temperature, then you can also use Simulink^{®}
Design Optimization™ software to help tune the values for *α* and
*BEX*.

**Surface-Potential-Based Model**

The surface-potential-based model includes temperature effects on the capacitance characteristics, as well as modeling the dependence of the transistor static behavior on temperature during simulation.

The **Measurement temperature** parameter on the **Main**
setting specifies temperature *T*_{m1} at which the other
device parameters have been extracted. The **Temperature Dependence** setting
provides the simulation temperature, *T*_{s}, and the
temperature-scaling coefficients for the other device parameters. For more information, see
Temperature Dependence (Surface-Potential-Based Modeling Option).

### Faults

The N-Channel MOSFET block models five types of fault:

`Open circuit`

— Failure due to metallization burnout`Drain-source short`

— Failure due to avalanche breakdown on drain-source channel`Drain-bulk short or source-bulk short`

— Failure due to avalanche breakdown on drain-bulk or source-bulk channels`Gate oxide short`

— Failure of the gate oxide dielectric layer`Parameter shift`

— Failure due to aging

The block can trigger fault events at a specific time or when the current or voltage exceed the limit for longer than a specific time interval.

To enable these trigger mechanisms, set the **Fault trigger** parameter to
either `Temporal`

or `Behavioral`

.

**Parameter Shift Fault**

If, in the **Faults** settings, you set the **Failure
mode** parameter to `Parameter shift`

, the MOSFET
fails due to the aging of its components. This equation defines the value of the shifted
parameters:

$$Parameter(t)=Paramete{r}_{faulted}-\left(Paramete{r}_{faulted}-Paramete{r}_{unfaulted}\right)\text{sech}\left(\frac{t-{t}_{th}}{\tau}\right),$$

where *t _{th}* is the time
threshold when the fault is triggered and

*τ*is the value of the

**Fault transition time constant, tau**parameter.

**Gate Oxide Short Fault**

If, in the **Faults** settings, you set the **Failure
mode** parameter to `Gate oxide short`

, the gate oxide
dielectric layer fails. These figures show the equivalent circuits for the three terminal
or four terminal MOSFET in the unfaulted and faulted state:

### Thermal Port

The block has an optional thermal port, hidden by default. To expose the thermal port, set the
**Modeling option** parameter to:

`Threshold-based with thermal`

— Model based on threshold voltage and with exposed thermal port`Surface-potential-based with thermal`

— Model based on surface potential and with exposed thermal port

This action displays the thermal port **H** on the block icon, and exposes
the **Thermal Port** parameters.

Use the thermal port to simulate the effects of generated heat and device temperature. For
more information on using thermal ports and on the **Thermal Port**
parameters, see Simulating Thermal Effects in Semiconductors.

### Variables

To set the priority and initial target values for the block variables prior to simulation,
use the **Initial Targets** section in the block dialog box or Property
Inspector. For more information, see Set Priority and Initial Target for Block Variables.

Nominal values provide a way to specify the expected magnitude of a variable in a model.
Using system scaling based on nominal values increases the simulation robustness. Nominal
values can come from different sources, one of which is the **Nominal
Values** section in the block dialog box or Property Inspector. For more
information, see System Scaling by Nominal Values.

This table shows the relationship between the capacitances of the block and the initial targets:

Defined Capacitance | Initial Targets |
---|---|

Gate-emitter capacitance, Cge | Set the initial target for the gate-emitter capacitance voltage only. Set the initial target of the collector-emitter capacitance voltage to `0` or set its priority to `None` . |

Collector-emitter capacitance, Cce | Set the initial target for the collector-emitter capacitance voltage only. Set the initial target of the gate-emitter capacitance voltage to `0` or set its priority to `None` . |

Gate-collector capacitance, Cgc | Set the initial targets for the gate-collector voltages by applying constraints on the gate-emitter and collector-emitter voltages. The initial condition of the gate-collector capacitance voltage is equal to the voltage between the gate-emitter and collector-emitter. |

Gate-emitter capacitance, Cge, and gate-collector capacitance, Cgc | Set the initial targets for the gate-emitter and gate-collector voltages by applying constraints on the gate-emitter and collector-emitter voltages. The initial condition of the gate-collector capacitance voltage is equal to the voltage between the gate-emitter and the collector-emitter. |

Gate-emitter capacitance, Cge, and collector-emitter capacitance, Cce | Set the initial target for the gate-emitter and the collector-emitter capacitance. |

Gate-collector capacitance, Cgc, and collector-emitter capacitance, Cce | Set the initial targets for the gate-collector and collector-emitter voltages by applying constraints on the gate-emitter and collector-emitter voltages. The initial condition of the gate-collector capacitance voltage is equal to the voltage between the gate-emitter and the collector-emitter. |

Gate-emitter capacitance, Cge, gate-collector capacitance, Cgc, and collector-emitter capacitance, Cce | Set the initial targets for the gate-emitter, gate collector and collector-emitter capacitances by applying constraints on the gate-emitter and collector-emitter voltages. The initial condition of the gate-collector capacitance voltage is equal to the voltage between the gate-emitter and the collector-emitter. |

**Note**

Inside your model, the number of initial targets with **Priority** equal to `Low`

or `High`

must match the number of differential variables. The differential variables come from the inductors and the capacitances in the model.

## Examples

## Assumptions and Limitations

When modeling temperature dependence for the threshold-based block modeling option, consider the following:

The block does not account for temperature-dependent effects on the capacitances.

When you specify

*R*at a second measurement temperature, it must be quoted for the same working point (that is, the same drain current and gate-source voltage) as for the other_{DS}(on)*R*value. Inconsistent values for_{DS}(on)*R*at the higher temperature will result in unphysical values for_{DS}(on)*α*and unrepresentative simulation results. Typically*R*increases by a factor of about 1.5 for a hundred degree increase in temperature._{DS}(on)You may need to tune the values of

*BEX*and threshold voltage,*V*_{th}, to replicate the*I*–_{DS}*V*relationship (if available) for a given device. Increasing_{GS}*V*moves the_{th}*I*-_{DS}*–V*plots to the right. The value of_{GS}*BEX*affects whether the*I*–_{DS}*V*curves for different temperatures cross each other, or not, for the ranges of_{GS}*V*and_{DS}*V*considered. Therefore, an inappropriate value can result in the different temperature curves appearing to be reordered. Quoting_{GS}*R*values for higher currents, preferably close to the current at which it will operate in your circuit, will reduce sensitivity to the precise value of_{DS}(on)*BEX*.

## Ports

### Conserving

## Parameters

## References

[1] Shichman, H. and D. A. Hodges. “Modeling and simulation of
insulated-gate field-effect transistor switching circuits.” *IEEE J. Solid State
Circuits*. SC-3, 1968.

[2] Van Langevelde, R., A. J. Scholten, and D. B .M. Klaassen.
"Physical Background of MOS Model 11. Level 1101."* Nat.Lab. Unclassified Report
2003/00239*. April 2003.

[3] Oh, S-Y., D. E. Ward, and R. W. Dutton. “Transient analysis
of MOS transistors.” *IEEE J. Solid State Circuits*. SC-15, pp.
636-643, 1980.

## Extended Capabilities

## Version History

**Introduced in R2008a**