Signal Conversion

Convert signal to new type without altering signal values

• Library:

• Simulink / Signal Attributes

  HDL Coder / Signal Attributes

• 

Description

The Signal Conversion block converts a signal from one type to another. To select the type of conversion to perform, use the Output parameter or one of these preconfigured Signal Conversion blocks:

• Signal Copy block

• To Virtual Bus block

• To Nonvirtual Bus block

Ports

Input

Port_1 — Input signal to convert

scalar | vector | matrix | N-D array

Input signal to convert, specified as a scalar, vector, matrix, or N-D array.

Data Types: single | double | half | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | string | Boolean | fixed point | enumerated | bus

Output

Port_1 — Converted signal

scalar | vector | matrix | N-D array

Output signal is the input signal converted to the specified type.

Data Types: single | double | half | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Parameters

Output — Type of conversion

Signal copy (default) | Virtual bus | Nonvirtual bus

Specify the type of conversion to perform. The type of conversion that you use depends on your modeling goal.

Modeling Goal	Output Option
Reduce generated code for a muxed signal. For an example involving Simulink® Coder™ software, see Generate Reentrant Code from Subsystems (Simulink Coder).	Signal copy
Connect a block with a constant sample time to an output port of an enabled subsystem.	Signal copy
Save memory by converting a nonvirtual bus to a virtual bus.	Virtual bus
Pass a virtual bus to a modeling construct that requires a nonvirtual bus, such as a Model block.	Nonvirtual bus

• The Signal copy option is the default. The type of conversion that the Signal Conversion block performs using the Signal copy option depends on the type of input signal.

  Type of Input Signal	Conversion That the Signal Copy Option Performs
  Muxed (nonbus) signal	Converts the muxed signal, whose elements occupy discontiguous areas of memory, to a vector signal, whose elements occupy contiguous areas of memory. The conversion allocates a contiguous area of memory for the elements of the muxed signal and copies the values from the discontiguous areas (represented by the block input) to the contiguous areas (represented by the block output) at each time step.
  Bus	Outputs a contiguous copy of the bus that is the input to the Signal Conversion block.

  For an array of buses input signal, use the Signal copy option.

• The Virtual bus option converts a nonvirtual bus to a virtual bus.

• The Nonvirtual bus option converts a virtual bus to a nonvirtual bus.

Programmatic Use

Block Parameter: ConversionOutput

Type: character vector

Values: 'Signal copy' | 'Virtual bus' | 'Nonvirtual bus'

Default: 'Signal copy'

Data type — Nonvirtual bus data type

Inherit: auto (default) | Bus: <object name> | <data type expression>

Specify the output data type of the nonvirtual bus that the Signal Conversion block produces.

This option is available only when you set the Output parameter to Nonvirtual bus.

The default option is Inherit: auto, which uses a rule that inherits a data type.

Specify a Simulink.Bus object in the Data type parameter for one or both of the following blocks:

• Signal Conversion block

• An upstream Bus Creator block

If you specify a bus object for the Signal Conversion block, but not for its upstream Bus Creator block, then use a bus object that matches the hierarchy of the bus that upstream Bus Creator block outputs.

If you specify a bus object for both the Signal Conversion block and its upstream Bus Creator block, use the same bus object for both blocks.

Click the Show data type assistant button to display the Data Type Assistant, which helps you set the data type attributes. For more information, see Specify Data Types Using Data Type Assistant.

Dependencies

To enable this parameter, set Output to Nonvirtual bus.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'Inherit: auto' | 'Bus: <object name>' | '<data type expression>'

Default: 'Inherit: auto'

Exclude this block from 'Block reduction' optimization — Exclude from block reduction optimization

off (default) | on

This option is available only when you set the Output parameter to Signal copy. If the elements of the input signal occupy contiguous areas of memory, then as an optimization, Simulink software eliminates the block from the compiled model. If you select the Exclude this block from 'Block reduction' optimization check box, the optimization occurs the next time you compile the model. For more information, see Block reduction.

Programmatic Use

Block Parameter: OverrideOpt

Type: character vector

Values: 'off' | 'on'

Default: 'off'

Model Examples

Create Contiguous Copy of a Bus Signal

Use the Signal Conversion block to create a contiguous copy of a bus signal.

Open Model

Convert Virtual Bus to a Nonvirtual Bus

In this example, the Signal Conversion block converts a virtual bus signal from the first Bus Selector block to a nonvirtual bus signal that inputs to the second Bus Selector block.

Open Model

Convert Nonvirtual Bus to Virtual Bus

In this example, the Signal Conversion block converts the nonvirtual bus signal from the Bus Creator block to a virtual bus signal that inputs to the Bus Selector block.

Open Model

Convert Muxed Signal to a Vector

Use the Signal Conversion block to convert a muxed input signal to a vector.

Open Model

Block Characteristics

Data Types	Boolean | double | enumerated | fixed point | half | integer | single | string
Direct Feedthrough	yes
Multidimensional Signals	yes
Variable-Size Signals	yes
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a pass-through implementation.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.