Simulink Block Considerations

R2026b

Names, math operations, ports and subsystems, signal routing, logic and bit operations

Apply high-integrity guidelines for Simulink^® block names, math operations, ports and subsystems, signal routing, and logic and bit operations.

Modeling Guidelines

Naming Conventions

hisl_0031: Model file names	Use naming conventions for model file names
hisl_0032: Model element names	Naming conventions for model elements that produce valid identifiers in generated code

Math Operations

hisl_0001: Usage of Abs block	Avoid unsupported data types and protect against integer overflow for the Abs block
hisl_0002: Usage of remainder and reciprocal operations	To support robustness of generated code, when using the Math Function block with remainder-after-division (`rem`) or reciprocal (`reciprocal`) operations
hisl_0003: Usage of square root operations	To support robustness of generated code, when using the Square Root operations
hisl_0028: Usage of Reciprocal Square Root blocks	Protect inputs of the Reciprocal Square Root block to avoid undesirable results in generated code
hisl_0004: Usage of natural logarithm and base 10 logarithm operations	Protect against invalid inputs to logarithm operations
hisl_0005: Usage of Product blocks	Protect divisor inputs from becoming singular matrices in Product blocks
hisl_0029: Usage of Assignment blocks	Initialize array fields before first use in the Assignment block to avoid undesirable results in generated code
hisl_0066: Usage of Gain blocks	Set the Gain block value to a nonzero value other than 1 to support traceability of generated code
hisl_0067: Protect against divide-by-zero calculations	Protect the divisor from going to zero in divide operations to improve robustness of generated code

Ports & Subsystems

hisl_0006: Usage of While Iterator blocks	Set maximum number of iterations for While Iterator blocks to support bounded iterative behavior
hisl_0007: Usage of For Iterator or While Iterator subsystems	Avoid using sample time-dependent blocks within For Iterator or While Iterator subsystems
hisl_0008: Usage of For Iterator blocks	Configure For Iterator blocks to support bounded iterative behavior in generated code
hisl_0010: Usage of If blocks and If Action Subsystem blocks	Connect If block outports to If Action Subsystem blocks and use else conditions to support verifiable generated code
hisl_0011: Usage of Switch Case blocks and Action Subsystem blocks	To support verifiable generated code, when using the Switch Case block
hisl_0024: Inport interface definition	Define data type, port dimensions, and sample time for inports to support strong typing and unambiguous model behavior
hisl_0025: Design min/max specification of input interfaces	Provide design minimum and maximum ranges for inport interfaces to support precise input interface specification
hisl_0026: Design min/max specification of output interfaces	Provide design minimum and maximum ranges for outport interfaces to support precise output interface specification
hisl_0075: Usage of library links	Avoid disabled and parameterized library links for consistent simulation and code generation (Since R2022a)
hisl_0077: Outport interface definition	Define data type, port dimensions, and sample time for outport interfaces (Since R2022b)
hisl_0078: Usage of identical modeling patterns	Account for identical and similar modeling patterns to reduce code complexity (Since R2024a)
hisl_0079: Connections to root input/output ports	Adhere to internal connection constraints on root-level Inport and Outport blocks to improve traceability (Since R2024a)

Signal Routing

hisl_0015: Usage of Merge blocks	Use Merge blocks with mutually exclusive conditionally executed subsystems to support unambiguous behavior
hisl_0021: Consistent vector indexing method	Use a consistent vector indexing method within a model to reduce the risk of indexing errors
hisl_0022: Data type selection for index signals	Use an appropriate data type for index signals to prevent unexpected results and enable correct data access
hisl_0023: Verification of variant blocks	Configure Variant block activation time to simplify consistency testing between a model and generated code
hisl_0034: Usage of Signal Routing blocks	Avoid the ~= operator on floating-point data types in Switch blocks to improve model robustness

Logic and Bit Operations

hisl_0016: Usage of blocks that compute relational operators	Avoid using equality and inequality operators on floating-point data types
hisl_0017: Usage of blocks that compute relational operators (2)	Configure relational operator blocks to produce unambiguous behavior in generated code
hisl_0018: Usage of Logical Operator block	Configure the Logical Operator block to produce unambiguous behavior in generated code
hisl_0073: Usage of bit-shift operations	Avoid shift operations greater than or equal to the bit-width to prevent violations of coding standards

Lookup Table Blocks

hisl_0033: Usage of Lookup Table blocks	Keep out-of-range protection enabled in Lookup Table blocks to protect against out-of-range inputs or indices
hisl_0072: Usage of tunable parameters for referenced models	Use Simulink.Parameter objects to define tunable parameters and prevent unintended loss of tunability
hisl_0073: Usage of bit-shift operations	Avoid shift operations greater than or equal to the bit-width to prevent violations of coding standards