setTriggerCondition

Configure each signal value comparison

Syntax

setTriggerCondition(DC,name,enable,value)

setTriggerCondition(DC,name,enable,value,N)

Description

Add-On Required: This feature requires one of these add-ons.

• HDL Verifier Support Package for Intel FPGA Boards
• HDL Verifier Support Package for AMD FPGA and SoC Devices

setTriggerCondition(DC,name,enable,value) configures a trigger value comparison for signal name in trigger stage 1. DC is a customized data capture object. The enable argument indicates whether this signal is part of the overall trigger condition.

setTriggerCondition(DC,name,enable,value,N) configures a trigger value comparison for signal name in a trigger stage specified by N. DC is a customized data capture object. The enable argument indicates whether this signal is part of the overall trigger condition.

Input Arguments

DC — Customized data capture object

hdlverifier.FPGADataReader System object™

Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

name — Name of trigger component signal

character vector

Name of trigger component signal, specified as a character vector.

This name must match one of the signal names configured on creation of the input System object DC. The signal must be configured as a possible trigger signal.

Data Types: char

enable — Indication that signal is part of trigger condition

true or 1 | false or 0

Indication that the signal is part of the trigger condition, specified as a numeric or logical 1 (true) or 0 (false). To use this signal in the overall trigger condition, set this value to 1 (true). When you set this value to 0 (false), the signal is not used for the overall trigger condition.

value — Value to compare this signal to as part of the trigger condition

decimal | binary | hexadecimal | 'Low' | 'High' | 'Rising edge' | 'Falling edge' | 'Both edges'

The trigger condition comprises value comparisons of one or more signals. This input specifies the value to match for each signal.

For a multibit signal, specify a decimal, binary, or a hexadecimal value within the range of the data type associated with the signal. While providing hexadecimal or binary values, you can provide values with a combination of X or x (don't care value) to enable bit masking. That means, while comparing the values, the trigger condition ignores the place values with X or x and provides the output.

To separate a group of bits for better readability, you can use _ between bits. For example, you can represent a 32-bit binary value as '0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXX' and a 32-bit hexadecimal value as '0xAB_CDEXFX'.

For logical signals, specify a string that indicates the level or edge to match. For more information, see Triggers.

N — Trigger stage

integer from 1 to M

Trigger stage, specified as an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool. Use N to set the trigger condition in Nth trigger stage. If you do not specify N, by default, the function sets the trigger condition in trigger stage 1.

Version History

Introduced in R2017a