Triggers

What Is a Trigger Condition?

A trigger condition is a logical statement that defines when to capture data from the FPGA. Use a trigger condition to capture data around an event of interest on the FPGA. Capture multiple occurrences of an event by setting Number of capture windows to the desired value. A trigger condition is composed of value comparison tests on one or more FPGA signals. For example:

counter == 100

All trigger comparisons are synchronous. When you specify an edge condition for a Boolean signal, the IP core compares the current sampled value with the sampled value from the previous clock cycle.

fifo_full == 'Rising edge' 

The trigger condition is met when all terms of the condition are true on the same clock cycle. You can use only a single value comparison per signal.

receiver_state == 3 OR message_detected == 'High'

fifo_cnt == 0 AND fifo_pop == 'High'

You can use only a single type of logical operator in the trigger condition. You cannot mix AND and OR conditions.

fifo_empty == 'Rising edge' OR fifo_full == 'Rising edge' OR memctrl_state == 2

receiver_state == 3 AND message_addr == 148 AND pkt_type == 5

You can use multiple comparison operators in the trigger condition.

fifo_empty == 'Rising edge' OR fifo_full != 'LOW' OR memctrl_state == 2

receiver_state == 3 AND message_addr > 148 AND pkt_type >= 5

You can use X or x (don't-care value) in the trigger condition. While comparing, the trigger condition ignores the place values with X. When the trigger condition is 0b1X1, the possible trigger condition values are 0b101 or 0b111.

receiver_state == 3 AND message_addr == 148 AND pkt_type == 0b1X1

Sequential Trigger

A sequential trigger enables you to give a set of trigger conditions in multiple stages to capture specified data from an FPGA. With a sequential trigger, you can read data to MATLAB^® or Simulink^® only after all of the specified trigger conditions happen in sequence. For multiple trigger stages, set the Max trigger stages parameter of the FPGA Data Capture Component Generator tool to a value greater than 1. Max trigger stages sets the maximum number of trigger stages for providing trigger conditions. For example, if Max trigger stages is 3, the Trigger tab in the FPGA Data Capture tool or in the FPGA Data Reader block can have maximum of 3 trigger stages.

Define a trigger condition by specific values matched on one or more signals in each stage. For example, if the number of trigger stages is 3 and 10 signals exist, you can set these trigger conditions.

• Trigger condition for stage 1:

  ((signal1 > 10) and (signal3 == true) and (signal7 < 5));

• Trigger condition for stage 2:

  ((signal1 == 0b0110) or (signal4 == 0XXX) or (signal8 < 5));

• Trigger condition for stage 3:

  ((signal2 != 5) and (signal6 == true) and (signal8 == 8));

Configure a Trigger Condition

At generation time, specify which signals you want to be available for use in trigger conditions. A signal can be a trigger without capturing data, or it can be both a trigger and a captured signal. You can modify the trigger condition at capture time, using any signals you specified as triggers. The data capture IP core on the FPGA receives the trigger definition from MATLAB and configures on-chip muxes to detect the event.

When you use the FPGA Data Capture tool, or the FPGA Data Reader block, set the trigger condition on the Trigger tab. Each line in the table is the value comparison for one signal. To combine the signal values, use the trigger combination operator. To show a signal on this tab, you must specify the signal as a trigger at generation time.

For an hdlverifier.FPGADataReader System object™, configure the trigger condition using the setTriggerCondition, setTriggerComparisonOperator, and setTriggerCombinationOperator object functions. To check your configuration, call the displayTriggerCondition object function.

If you do not enable a trigger condition on any signal, the data capture IP core captures data immediately.

Trigger Position

You can change the relative position of the trigger detection cycle within the capture buffer. Use this feature to capture the relevant data, whether it is before or after the trigger event.

Suppose you want to debug the rates of pushes and pops to a FIFO design. You can set a trigger on a High value of the signals fifo_empty or fifo_full.

By default, the clock cycle when the trigger is detected is the first sample of the capture buffer. The IP core captures a buffer starting from the cycle when fifo_full changes to high.

To debug the fifo_full condition, observe the signals before the trigger condition occurs. In the capture settings, change the Trigger position to 3/4 of the window depth using the tic mark on the slider. For example, if Sample depth is 128, Number of capture windows is 1, and Number of trigger stages is 1, then window depth is 128. The trigger event is at sample 96 of that window. The IP core captures a buffer that contains 96 samples before the trigger event, and 36 samples after the trigger event. This setting captures data that shows the lead-up to the trigger event, and the aftermath. The location of the trigger event is shown with the vertical cursor at fifo_full.

You can set the Trigger position to a number of samples between 0 and the window depth-1, inclusive. When you set the trigger position equal to window depth-1, the last sample corresponds to the cycle when the trigger occurs.

To observe more than one occurrence of the trigger event, change the Number of capture windows to the desired number.

In this example, Number of capture windows is 4, Number of trigger stages is 1, Sample depth is 128, and Trigger position is 0. HDL IP captures four windows, where each window depth is 32 samples, starting when fifo_full changes to high.