Xilinx RFSoC Devices

Generate and deploy HDL code and embedded software on Xilinx^® RFSoC Devices

HDL Coder™ can generate an IP core, integrate it into your Vivado^® project, and program the Xilinx RFSoC hardware.

To deploy your design to the Xilinx RFSoC hardware, you must install the HDL Coder Support Package for Xilinx RFSoC Devices. For installation information, see HDL Coder Supported Hardware.

Classes

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Board and Workflow

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

Functions

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Export Reference Design

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor

Add Interfaces

`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addAXI4SlaveInterface`	Add and define AXI4 slave interface
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface

Board and Reference Design

`addCustomVivadoDesign`	Specify Xilinx Vivado exported block design Tcl file
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

Callback Functions

`CallbackCustomProgrammingMethod`	Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
`EmbeddedCoderSupportPackage`	Specify whether to use an Embedded Coder support package
`PostBuildBitstreamFcn`	Function handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
`PostCreateProjectFcn`	Function handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
`PostSWInterfaceFcn`	Function handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
`PostTargetInterfaceFcn`	Function handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
`PostTargetReferenceDesignFcn`	Function handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor

Related Information

HDL Coder Support Package for Xilinx RFSoC Devices
Generate IP Core and Bitstream
Create a Custom Hardware Platform
RF Data Converter Configuration (HDL Coder Support Package for Xilinx RFSoC Devices)
System Object Usage (HDL Coder Support Package for Xilinx RFSoC Devices)

Featured Examples

DAC and ADC Loopback Data Capture

Capture raw analog-to-digital converter (ADC) data using the FPGA I/O API from the Xilinx® Zynq® UltraScale+™ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit. This example uses the HDL Workflow Advisor to configure an SoC model for HDL code generation. In this example, you generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.

Open Script

IQ Mixer Mode Capture

Enable the RFSoC built-in numerically-controlled oscillator (NCO) mixer. The mixer design uses a different data format that, instead of providing real signals, provides a complex in-phase and quadrature (IQ) signal to a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). There is more data to transfer to direct memory access (DMA) and back to MATLAB® given that you need to transfer I and Q samples back. You can accommodate this larger data width by increasing the DMA data width to 128 bits.

Open Script

PL-DDR4 ADC Data Capture

Perform analog-to-digital converter (ADC) data captures with programmable logic (PL) double data rate 4 (DDR4) memory.

Open Script

DAC PL-DDR4 Transmit

Transmit waveforms out of the digital-to-analog converter (DAC) that is read from programmable logic (PL) double data rate 4 (DDR4) memory. Using PL-DDR4 memory offers advantages such as the ability to access 4 gigabytes of memory space. This amount of memory can help facilitate applications requiring large waveform transmissions that are not normally feasible with FPGA block random access memory (BRAM). This figure shows the relevant intellectual property (IP) interfaces and connectivity that are used in this design.

Open Script

Polyphase Channelizer

Use the HDL-optimized Channelizer block to process incoming analog-to-digital converter (ADC) samples and produce a spectrum that has 512 MHz of bandwidth. MATLAB® displays the resulting spectrum plot by using FPGA API functions over a TCP/IP connection. The channelizer data sent back is in limited bursts, which are triggered by an AXI4 register in a capture loop. The model also contains an interface to the digital-to-analog converter (DAC) by using a numerically-controlled oscillator (NCO) to drive a tone commanded at some frequency over AXI4.

Open Script

Multi-Tile Synchronization

Use multi-tile synchronization (MTS) to resolve the time alignment issue of multiple channels across different tiles on an RFSoC device. The RFSoC has built-in features that enforce the time alignment for samples of multiple channels across different tiles. Channels in a tile alone are aligned in time but a guarantee of alignment with another channel from a different tile does not exist. You can enable multi-tile synchronization (MTS) to correct for this issue by first measuring latency across different tiles and then applying sample delays to ensure samples align correctly.

Open Script