This example illustrates how to automatically insert the JTAG MATLAB as AXI Master IP into your reference design, and use MATLAB to prototype your HDL Coder generated FPGA IP Core.
To access onboard memory locations and quickly probe or control the FPGA logic from MATLAB, use the JTAG MATLAB as AXI master IP. The object connects to the IP over a physical JTAG cable, and allows read and write commands to slave memory locations from the MATLAB command line.
You can insert the JTAG MATLAB as AXI Master IP when running the Set Target Reference Design task of the
IP Core Generation workflow.
To use this capability:
You must have the HDL Verifier™ hardware support packages installed and downloaded.
You must not target standalone boards that do not have the hRD.addAXI4SlaveInterface or boards that are based on Xilinx ISE.
This example uses the ZedBoard™. Before you run the workflow, you must:
Install Xilinx Vivado™ Design Suite, with supported version listed in the HDL Coder documentation
Setup the Zynq board for the JTAG MATLAB as AXI Master IP insertion. To learn how to set up the ZedBoard, refer to the Set up Zynq hardware and tools section in the Getting Started with HW/SW Co-design Workflow for Xilinx Zynq Platform example.
Download and install the HDL Verifier hardware support package for Xilinx FPGA Boards. See setup and configuration section in HDL Verifier Support Package for Xilinx FPGA Boards.
Set up the path to the synthesis tool by using hdlsetuptoolpath. as shown below:
hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2018.3\bin\vivado.bat');
1. Open hdlcoder_led_blinking demo using following command:
2. Open the HDL Workflow Advisor from the
hdlcoder_led_blinking/led_counter subsystem by right-clicking the
led_counter subsystem, and choosing HDL Code > HDL Workflow Advisor.
3. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.
4. For Target platform, select ZedBoard. If you don't have this option, select Get more to open the Support Package Installer. In the Support Package Installer, select Xilinx Zynq™ Platform and follow the instructions provided by the Support Package Installer to complete the installation.
5. Click Run This Task to run the Set Target Device and Synthesis Tool task.
6. In the Set Target > Set Target Reference Design task, choose Default system and set Insert JTAG MATLAB as AXI Master dropdown choice to on which is present in the reference design parameter options.
7. Click Run This Task to run the Set Target Reference Design task.
Map each port in your DUT to one of the IP core target interfaces. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4-Lite interface, so HDL Coder generates AXI interface accessible registers for them. The LED output port is mapped to an external interface, LEDs General Purpose [0:7], which connects to the LED hardware on the Zynq board.
1. In the Set Target > Set Target Interface task, choose
AXI4-Lite for Blink_frequency, Blink_direction, and Read_back.
LEDs General Purpose [0:7] for LED.
3. Create the reference design project which includes JTAG MATLAB as AXI Master.
To create the project, right-click the Create Project task and select Run to Selected Task.
"In the Vivado project, you see the JTAG MATLAB as AXI Master IP inserted in the reference design".
In order to use this feature, you require a HDL Verifier license. After that a simple MATLAB® command line interface can be used to access the IP core generated by HDL Coder.
In the MATLAB command window:
1. Create the AXI master object
h = aximaster('Xilinx')
2. Input a write command to change the LED Blinking frequency
Observe the LED blinking frequency is low. Try change the value in AXI Master write command from 0 to 15 to increase the LED blinking frequency.
3. Input a read command to read the current counter value
4. Delete the object when done to free up the JTAG resource. If the object is not deleted, other JTAG operations such as programming the FPGA will fail.
This demonstration shows how you can easily prototype your FPGA IP core from MATLAB.
The "Insert JTAG MATLAB as AXI Master(HDL Verifier required)" reference design parameter is by default added to your custom reference design. The default value for the parameter is "off".
If you want to control these default behaviour for your reference design, you can use following two optional reference design properties:
AddJTAGMATLABasAXIMasterParameter and JTAGMATLABasAXIMasterDefaultValue where the reference design author can set those properties to turn off or even disable the parameter option to not to appear in HDL Workflow Advisor.
% Insert JTAG MATLAB as AXI Master in reference designs hRD.AddJTAGMATLABasAXIMasterParameter = true; hRD.JTAGMATLABasAXIMasterDefaultValue = 'on';
1. Parameter visibility option in HDLWA: If you don't want the JTAG MATLAB as AXI Master IP to be inserted in the reference design that you authored, disable this property: hRD.AddJTAGMATLABasAXIMasterParameter to false.
2. Default value of parameter: In the reference design that you authored, you can control the property hRD.JTAGMATLABasAXIMasterDefaultValue to 'on' or 'off'.