This example shows how to use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. This example uses MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated DUT registers by enabling the reference design parameter option Insert JTAG MATAB as AXI Master. You can then access DUT registers from MATLAB directly. Alternatively, you can use Xilinx JTAG AXI Master to access the DUT registers using Vivado Tcl Console by writing Tcl commands. For Xilinx JTAG AXI Master, you need to create a custom reference design. The FPGA design is implemented on the Xilinx Kintex-7 KC705 board.
Xilinx Vivado Design Suite, with supported version listed in the HDL Coder documentation
Xilinx Kintex-7 KC705 development board
HDL Coder™ support package for Xilinx FPGA Boards
(Optional) HDL Verifier™ support package for Xilinx FPGA Boards
There are many designs which will benefit from using the HDL Coder™ IP Core Generation Workflow without using either an embedded ARM® processor or an Embedded Coder™ Support Package, but which still leverages the HDL Coder generated AXI4-Lite registers. These designs include:
HDL Verifier™ MATLAB as AXI Master + HDL Coder™ IP Core
Xilinx JTAG Master + HDL Coder™ IP Core
MicroBlaze™ + HDL Coder™ IP Core
PCIe Endpoint + HDL Coder™ IP Core
There are two reference designs included in this example:
Default system reference design uses MathWorks IP and a MATLAB command line interface for issuing read and write commands by enabling the reference design parameter option "Insert JTAG MATAB as AXI Master". Note that to use this parameter, you must have HDL Verifier™ installed.
Xilinx JTAG to AXI Master reference design uses Vivado IP for the JTAG to AXI Master and therefore requires using the Vivado Tcl console to issue reads and writes.
The two reference designs are nearly identical, except for the JTAG Master IP used in the block diagram shown below:
The reference design, "Xilinx JTAG to AXI Master", uses Vivado™ IP for the JTAG to AXI Master and therefore requires using the Vivado™ Tcl console to issue reads and writes:
Specify Insert JTAG MATLAB as AXI Master (HDL Verifier Required) to on in the Set Target Reference Design task of
IP Core Generation workflow. This adds MATLAB AXI Master IP automatically into the reference design and connects to the DUT IP using AXI4 slave interface. The detailed steps to auto insert the MATLAB JTAG AXI Master in the reference design are discussed in the following section.
The following instructions in this section applies to
Default System reference design which uses
MATLAB JTAG as AXI Master. Using this reference design, you can generate an HDL IP Core that blinks LEDs on the KC705 board.
1. Set up the Xilinx Vivado™ tool path by using the following command:
hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2019.1\bin\vivado.bat');
Use your own Xilinx Vivado™ installation path when executing the command.
2. Open the Simulink model that implements LED blinking using the command:
3. Launch HDL Workflow Advisor from the
hdlcoder_led_blinking/led_counter subsystem by right-clicking the
led_counter subsystem, and selecting HDL Code > HDL Workflow Advisor.
4. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select
IP Core Generation, For Target platform , select
Xilinx Kintex-7 KC705 development board and Click Run This Task to run the Set Target Device and Synthesis Tool task
5. In the Set Target > Set Target Reference Design task, Choose
Default System as reference design and set
Insert JTAG MATLAB as AXI Master dropdown choice to
on which is present in the reference design parameter options.
6. In the Set Target > Set Target Interface task, choose
AXI4-Lite for Blink_frequency, Blink_direction, and Read_back. Choose
LEDs General Purpose [0:7] for LED.
7. Run the remaining steps in the workflow to generate a bitstream and program the target device.
Notice that unlike the Zynq-based reference design, there is no Generate Software Interface Model task. This is shown in the following figure.
The base address for an HDL Coder™ IP Core is defined as
0x40000000 for the
Default System reference design which uses MATLAB AXI Master IP. You can see this in the generated IP Core report as shown in the following figure.
The offsets can be found in the IP Core Report Register Address Mapping table:
If HDL Verifier support package for Xilinx FPGA boards is installed and the reference design "MATLAB as AXI Master" reference design is selected, then a simple MATLAB command line interface can be use to access the IP core generated by HDL Coder.
1. create the AXI master object
h = aximaster('Xilinx')
2. Issue a simple write command. For example, to disable the DUT
3. To re-enable the DUT, use the following write command
4. Issue a read command. For example, to read the current counter value
5. Delete the object when done to free up the JTAG resource. If the object is not deleted, other JTAG operations such as programming the FPGA will fail.
You need to create a custom reference design to use Xilinx JTAG AXI Master in reference design and then add the reference design files to the MATLAB path using
To access the HDL Coder™ IP Core registers using Xilinx JTAG AXI Master, the base address is defined in reference design plugin file.
This example will use the stand alone Vivado Tcl console for the basic commands to issue reads and writes. The following commands can be used to open the JTAG device and setup an 'enable' and 'disable' write to the DUT. These can be entered directly into the Vivado Tcl console or saved in a Tcl file and sourced. For simplicity, copy the following Tcl commands into a file "open_jtag.tcl":
# Open connection to the JTAG Master open_hw connect_hw_server open_hw_target refresh_hw_device [lindex [get_hw_devices] 0]
# Create some reads/writes create_hw_axi_txn wr_enable [get_hw_axis hw_axi_1] -address 44a0_0004 -data 0000_0001 -type write create_hw_axi_txn wr_disable [get_hw_axis hw_axi_1] -address 44a0_0004 -data 0000_0000 -type write
Now launch the Vivado™ Tcl console, sourcing the file you just created:
>> system('vivado -mode tcl -source open_jtag.tcl&')
When you are done using the JTAG Master, close the connection using the following Tcl commands:
# Close and disconnect from the JTAG Master close_hw_target; disconnect_hw_server;
Using a JTAG to AXI Master is a simple way to interface with HDL Coder™ IP core registers in systems which do not have an embedded ARM® processor, such as the Kintex-7. This can be used as first step to debug stand alone HDL Coder™ IP cores, used prior to hand coding software for soft processors, such as MicroBlaze™, or as an easy way to tune parameters on a running system.