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Generate VHDL Code with Record Types for Bus Signals

For a Simulink® model that contains the bus signals at the subsystem interface, you can generate code with a VHDL® construct record type for those bus signals. Use the record type to simplify your VHDL code. The record type is especially useful for simplifying interfaces and maintaining a large number of signals at the entity level.

To generate code with record types for bus signals, enable the Generate Record types for Bus parameter. This parameter is available in the Configuration Parameter dialog box, in the HDL Code Generation > Global Settings > Coding Style > RTL Style section.

HDL Coder™ generates record types for:

  • Bus signals at design-under-test (DUT) interfaces

  • Bus signals at different subsystem-level interfaces

  • Bus signals at black box interfaces

  • Bus signals at controlled subsystem interfaces

  • Nested bus signals

  • Bus signals that have different data types

Requirements

  • To generate code with record types, set the target language to VHDL. Specify the Target language option in the HDL Code Generation pane of the Configuration Parameter dialog box.

  • When you create a bus in your model, the Bus object must be specified. You can create the Bus object by using the Type Editor tool. To open Type Editor, run this command in the MATLAB Command Window:

    typeeditor
    After you create a Bus object and specify its attributes, you can associate it with any block that needs to use the bus definition that the object provides. To associate a block with a bus, in the Block Parameters dialog box, set Output data type or Data type to Bus: <object name>, replacing <object name> with the Bus object name. For more information, see Specify Bus Properties with Simulink.Bus Object Data Types.

Use Record Types for Bus in HDL Code Generation

By default, the Generate Record types for Bus option is disabled. The generated code does not have record types. The bus signals are flattened at the interface and are defined as individual ports in an entity in the generated code.

If your model contains the non-virtual bus signals at the DUT interface or different subsystem-level interface, you can generate the VHDL code with record types for those bus signals.

For example, consider a Simulink model that has a bus signal at the DUT interface. In this example, the DUT subsystem consists of a Unit Delay block. The input and output of the block is a bus. This bus has two bus elements with the double datatype.

Simulink model that has Bus signals at DUT interface

To generate record types for the bus signals in the HDL code of your DUT subsystem:

  1. Create a Bus object by using the Type Editor tool.

  2. Specify Output data type as the Bus object in the Bus Creator block. For more information, see Create and Specify Simulink.Bus Objects.

  3. Specify Target language as VHDL.

  4. Enable the generation of record types for bus. In the configuration parameter dialog box, go to the HDL Code Generation > Global Settings > Coding Style > RTL Style section, select Generate Record types for Bus.

  5. Generate HDL code for the DUT subsystem. In the HDL Code tab, set Code for subsystem to the DUT subsystem, and then click the Generate HDL Code button.

You can also generate HDL code for your DUT with record types by setting the GenerateRecordType argument of the makehdl function to ''on''.

makehdl(<DUT>,GenerateRecordType="on");

Generated VHDL Code for DUT Subsystem with Record Type

HDL Coder defines the record type for bus signals in the VHDL package file. HDL Coder uses this package file for the port declaration of the bus signals in an entity.

This code snippet shows the VHDL code of a package file that specifies record types for two bus signal. The package file defines the record dataBus_record, which consists of two bus elements with the double data type.

-- --------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

PACKAGE DUT_pkg IS
  TYPE dataBus_record IS RECORD
    signal1           : std_logic_vector(63 DOWNTO 0);
    signal2           : std_logic_vector(63 DOWNTO 0);
  END RECORD dataBus_record;

END DUT_pkg;

These VHDL code of the DUT subsystem uses these record types for port declaration of the bus signals. This code snippet shows VHDL code for a DUT subsystem with record types for a bus signal:

-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.Subsystem_pkg.ALL;

ENTITY DUT IS
  PORT( clk              :   IN    std_logic;
        reset            :   IN    std_logic;
        clk_enable       :   IN    std_logic;
        In1              :   IN    dataBus_record;  -- record {double,double}
        ce_out           :   OUT   std_logic;
        Out1             :   OUT   dataBus_record  -- record {double,double}
        );
END DUT;

ARCHITECTURE rtl OF Subsystem IS

  -- Signals
  SIGNAL enb             : std_logic;
  SIGNAL In1_signal1     : std_logic_vector(63 DOWNTO 0);  -- ufix64
  SIGNAL In1_signal2     : std_logic_vector(63 DOWNTO 0);  -- ufix64
  SIGNAL signal1         : std_logic_vector(63 DOWNTO 0);  -- ufix64
  SIGNAL signal2         : std_logic_vector(63 DOWNTO 0);  -- ufix64
  SIGNAL Unit_Delay_out1 : dataBus_record;  -- record {double,double}

BEGIN
  In1_signal1 <= In1.signal1;
  In1_signal2 <= In1.signal2;

  enb <= clk_enable;

  Unit_Delay_1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      signal1 <= X"0000000000000000";
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        signal1 <= In1_signal1;
      END IF;
    END IF;
  END PROCESS Unit_Delay_1_process;

  Unit_Delay_2_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      signal2 <= X"0000000000000000";
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        signal2 <= In1_signal2;
      END IF;
    END IF;
  END PROCESS Unit_Delay_2_process;

  Unit_Delay_out1.signal1 <= signal1;
  Unit_Delay_out1.signal2 <= signal2;

  ce_out <= clk_enable;
  Out1 <= Unit_Delay_out1;

END rtl;

Limitations

  • HDL Coder does not generate record types for bus signals at a model reference interface.

  • HDL test bench generation does not support the record type when you disable the Use file I/O to read/write test bench data option.

  • HDL test bench generation does not support the record type when you enable the SystemVerilog DPI test bench option.

  • You cannot generate a cosimulation model for record types.

  • Target IP core generation does not support ports with the record type.

  • When your model contains the bus elements of complex or enumerated types, HDL Coder generates code without record types for these buses.

  • You cannot generate HDL Code with record types if your model contains a nested bus that has array of buses.

See Also

Functions

Objects

Apps

Related Topics