Improve the timing and increase the clock speed of your design for a target FPGA or SoC device by reducing the critical path. You can reduce the critical path by using different pipelining methods. For an overview on speed optimizations, see Speed and Area Optimizations in HDL Coder.
- Adaptive Pipelining
Automatic pipeline insertion based on the target device, target frequency, and multiplier word-lengths.
- Clock-Rate Pipelining
Pipeline registers insertion at the faster clock rate instead of the slower data rate.
- Distributed Pipelining
Definition, benefits, and costs of distributed pipelining.
- Distributed Pipelining Using Synthesis Timing Estimates
Use synthesis timing estimates for distributed pipelining to more accurately reflect how components function on hardware to better distribute pipelines and increase clock frequency for your target device.
- Constrained Output Pipelining
Constrained output pipelining definition and use case.
- Automatic Iterative Optimization
How automatic iterative optimization works, prerequisites and restrictions.
- Critical Path Estimation Without Running Synthesis
Find the estimated critical paths in your design without using third-party synthesis tools.
- Design Patterns That Require Adaptive Pipelining
For certain design patterns, you must enable the adaptive pipelining optimization to meet the timing requirements.
- Use Distributed Pipelining Optimization in Models with MATLAB Function Blocks
How to optimize HDL code for MATLAB Function blocks for speed by distributing design delays and generated pipeline stages.
- HDL Optimizations Across MATLAB Function Block Boundary Using MATLAB Datapath Architecture
Apply optimizations inside and across MATLAB Function blocks with other Simulink® blocks.
Learn how to resolve simulation mismatch issues when using pipeline optimizations with feedback loops.