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Guidelines for Speed and Area Optimizations

Guidelines for optimizing your design for speed and area for deployment to the target FPGA device

The HDL modeling guidelines are a set of recommended guidelines for creating Simulink® models, MATLAB Function blocks, and Stateflow® charts for code generation with HDL Coder™. In addition to providing architectural guidance, because the generated code targets hardware platforms such as FPGAs, ASICs, and SoCs, you can use these guidelines to optimize your design for speed or area on the target hardware.


List of Guidelines and Severity Levels

Guidelines for Area Optimizations

Guidelines for Speed Optimizations

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