Speed and Area Optimization

Improvements through resource sharing, streaming, pipelining, RAM mapping

Functions

`coder.hdl.loopspec`	Unroll or stream loops in generated HDL and SystemC code
`coder.hdl.pipeline`	Insert pipeline registers at output of MATLAB expression

Topics

Optimization Basics

Speed and Area Optimizations in HDL Coder
Learn about various speed and area optimizations and how to optimize your design.
Specify the Clock Enable Rate
Configure clock enable to run at design base rate or input data rate.
Minimize Clock Enables
Generate code for registers without clock enables.
Constant Multiplier Optimization
What is Constant multiplier optimization and how to specify this optimization.

Area Optimization

Map Persistent Arrays and dsp.Delay to RAM
In the HDL Workflow Advisor, select MATLAB to HDL Workflow > Code Generation > Optimizations tab.
Map Matrices to ROM
To map a matrix constant to ROM:If your MATLAB^® code meets these requirements, HDL Coder™ inserts a no-reset register at the output of the matrix in the generated code.
RAM Mapping for MATLAB Code
RAM mapping is an area optimization that maps storage and delay elements in your MATLAB code to RAM.
RAM Mapping Comparison for MATLAB Code
hdl.RAM, dsp.Delay, persistent array variables, and user-defined System object™ private properties can map to RAM, but have different attributes.

Speed Optimization

Pipelining MATLAB Code
Pipelining helps achieve a higher maximum clock rate by inserting registers at strategic points in the hardware to break the critical path.
Pipeline MATLAB Expressions
Insert registers at output of MATLAB expression.
Optimize MATLAB Loops
Optimize loops for area or speed.
Distributed Pipelining
Distributed pipelining definition, benefits, and costs.

Featured Examples

Optimize Clock Speed for MATLAB Code by Using Adaptive Pipelining

Use the adaptive pipelining optimization in HDL Coder to optimize clock speed for a MATLAB design.

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Distributed Pipelining for Clock Speed Optimization

Use the distributed pipelining and loop unrolling optimizations in HDL Coder to optimize clock speed.

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Map Matrices to Block RAMs to Reduce Area

Use the RAM mapping optimization in HDL Coder™ to map persistent matrix variables to block RAMs in hardware.

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Resource Sharing of Multipliers to Reduce Area

Use the resource sharing optimization in HDL Coder™. This optimization identifies functionally equivalent multiplier operations in MATLAB® code and shares them in order to optimize design area. You have control over the number of multipliers to be shared in the design.

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Loop Streaming to Reduce Area

Use the design-level loop streaming optimization in HDL Coder™ to optimize area.

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Constant Multiplier Optimization to Reduce Area

Perform a design-level area optimization in HDL Coder™ by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques. The CSD representation of multiplier constants for example, in gain coefficients or filter coefficients) significantly reduces the area of the hardware implementation.

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