addAXI4StreamInterface

Write data to IP core or read data from IP core using AXI4-Stream interface

Since R2020b

Syntax

addAXI4StreamInterface(hFPGA)

addAXI4StreamInterface(hFPGA, Name,Value)

Description

addAXI4StreamInterface(hFPGA) adds an AXI4-Stream interface that you can use to control the DUT ports mapped to AXI4-Stream interfaces in the HDL Coder™ generated IP core from MATLAB^®.

addAXI4StreamInterface(hFPGA, Name,Value) adds an AXI4-Stream interface that you can use to control the DUT ports mapped to AXI4-Stream interfaces in the HDL Coder generated IP core from MATLAB, with one or more properties specified as name-value pair arguments. Enclose each property and value pair in single quotes.

Examples

Add AXI4-Stream Interface to Control HDL IP Core

Add an AXI4-Stream interface to control HDL IP core generated for a Xilinx^® target.

Create a target object, hFPGA, for a Xilinx target.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4-Stream interface to the hFPGA object by using the addAXI4StreamInterface function.

addAXI4StreamInterface(hFPGA, ...
    ... % Interface properties
    "InterfaceID", "AXI4-Stream", ...
    "WriteEnable", true, ...
    "ReadEnable", true, ...
    "WriteFrameLength", 1024, ...
    "ReadFrameLength", 1024, ...
    ... % Driver properties
    "WriteDeviceName", "mwipcore0:mm2s0", ...
    "ReadDeviceName", "mwipcore0:s2mm0",...
    "WriteDataWidth", 32, ...
    "ReadDataWidth", 32);

After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to AXI4-Stream Interfaces.

Add AXI4-Stream Interface with Only Write Channel

Add an AXI4-Stream interface for a Xilinx target with only a write channel.

Create a target object, hFPGA, for a Xilinx target.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4-Stream interface to the hFPGA object by using the addAXI4StreamInterface function. Set ReadEnable to false.

addAXI4StreamInterface(hFPGA, ...
    ... % Interface properties
    "InterfaceID", "AXI4-Stream", ...
    "ReadEnable", false, ...
    "WriteFrameLength", 1024, ...
    ... % Driver properties
    "WriteDeviceName", "mwipcore0:mm2s0");

After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to AXI4-Stream Interfaces.

Input Arguments

hFPGA — Target FPGA object

fpga object

fpga object for the target vendor, specified as an fpga object.

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example: addAXI4StreamInterface(hFPGA, "InterfaceID", "AXI4-Stream") creates an AXI4-Stream interface with InterfaceID as AXI4-Stream.

InterfaceID — Name of AXI4-Stream interface

"AXI4-Stream" | string

Name of AXI4-Stream interface that you want to map the DUT ports to, specified as a string.

WriteEnable — Write channel enable signal

true (default) | false

Write channel enable signal, specified as either true or false. By default, WriteEnable is true, and you can write data into the slave channel of the AXI4-Stream interface on the IP core.

ReadEnable — Read channel enable signal

true (default) | false

Read channel enable signal, specified as either true or false. By default, ReadEnable is true, and you can read data from the master channel of the AXI4-Stream interface on the IP core.

WriteDeviceName — IIO device to write data

"mwipcore0:mm2s0" (default) | string array

Name and path of the IIO core device that you want to write to, specified as a string. When you generate the IP core by using the IP Core Generation workflow, the default name is mwipcore0:mmw2s0.

ReadDeviceName — IIO device to read data

"mwipcore0:s2mm0" (default) | string array

Name and path of the IIO device that you want to read from. When you generate the IP core by using the IP Core Generation workflow, the default name is mwipcore0:s2mm0.

WriteFrameLength — Write channel frame length

1024 (default) | scalar

Size of the data vector to be written to the IIO device, specified as a scalar. Use this parameter to determine the number of samples written for each DMA transfer.

ReadFrameLength — Write channel frame length

1024 (default) | scalar

Size of the data vector that is read from the IIO device, specified as a scalar. Use this parameter to determine the number of samples read for each DMA transfer.

WriteTimeout — Timeout for AXI4-Stream write

0 (default) | scalar

Maximum timeout for the AXI4-Stream write, specified as a scalar.

ReadTimeout — Timeout for AXI4-Stream read

0 (default) | scalar

Maximum timeout for the AXI4-Stream read, specified as a scalar.

WriteDataWidth — Write channel data width

32 (default) | 8 | 16 | 32 | 64 | 128

Write channel data width, specified as an integer.

Example: 'WriteDataWidth',32 specifies write channel data width of 32 bits.

ReadDataWidth — Read channel data width

32 (default) | 8 | 16 | 32 | 64 | 128

Read channel data width, specified as an integer.

Example: 'ReadDataWidth',32 specifies read channel data width of 32 bits.

FrameProcessingOrder — Data processing order

"RowMajor" (default) | "ColumnMajor"

Data processing order, specified as a string. Use this argument only when the input data is in matrix form.

Example: 'FrameProcessingOrder',"RowMajor"

Data Types: char | string

Version History

Introduced in R2020b