Custom Board and Reference Design
HDL Coder™ can generate an IP core that you can deploy to the Microchip FPGA boards. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you can register for the board.
|Define external IO interface for board object|
|Define external port interface for board object|
|Add and define internal IO interface between generated IP core and existing IP cores|
|Add and define AXI4 slave interface|
|Add clock and reset interface|
Board and Reference Design
|Specify Microchip Libero SoC exported block design Tcl file (Since R2022b)|
|Import microcontroller subsystem (MSS) in Microchip Libero Smart design (Since R2022b)|
|Check property values in reference design object|
|Check property values in board object|
- Board and Reference Design Registration System
System for defining and registering boards and reference designs.
- Register a Custom Board
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
- Register a Custom Reference Design
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
- Define and Add IP Repository to Custom Reference Design
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.