Custom Board and Reference Design

R2026b

Define and register custom reference design or custom board for Altera^® SoC device

HDL Coder™ can generate an IP core that you can deploy to the Altera FPGA and SoC boards. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you can register for the board.

Classes

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Board and Workflow

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

Functions

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Export Reference Design

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor

Add Interfaces

`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addRegisterInterface`	Add and define register interface using AXI4 and AXI4-Lite protocol
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface

Board and Reference Design

`addCustomQsysDesign`	Specify Altera Qsys project file
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`addSupportedTool`	Add supported synthesis tool to a board (Since R2026b)
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

Callback Functions

`CallbackCustomProgrammingMethod`	Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
`PostBuildBitstreamFcn`	Function handle for callback function that gets executed after the build FPGA bitstream task runs
`PostCreateProjectFcn`	Function handle for callback function that gets executed after the create project task runs
`PostSWInterfaceFcn`	Function handle for custom callback function that gets executed after the generate software interface task runs
`PostTargetInterfaceFcn`	Function handle for callback function that gets executed after the set target interface task runs
`PostTargetReferenceDesignFcn`	Function handle for callback function that gets executed after the target reference design is set

Topics

Board and Reference Design Registration System
System for defining and registering boards and reference designs.
Register a Custom Board
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Register a Custom Reference Design
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Define Custom Parameters and Callback Functions for Custom Reference Design
Learn how to define custom parameters and custom callback functions for your custom reference design.
Define and Add IP Repository to Custom Reference Design
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.