addAXI4StreamInterface
Class: hdlcoder.ReferenceDesign
Namespace: hdlcoder
Syntax
addAXI4StreamInterface('MasterChannelConnection',Master_Channel_Port,'SlaveChannelConnection',Slave_Channel_Port)
addAXI4StreamInterface('MasterChannelConnection',Master_Channel_Port,'SlaveChannelConnection',Slave_Channel_Port), Name,Value
Description
addAXI4StreamInterface('MasterChannelConnection',
adds an AXI4-Stream interface to an Master_Channel_Port
,'SlaveChannelConnection',Slave_Channel_Port
)hdlcoder.ReferenceDesign
object.
addAXI4StreamInterface('MasterChannelConnection',
adds and defines an AXI4-Stream interface, with additional options specified by one or
more Master_Channel_Port
,'SlaveChannelConnection',Slave_Channel_Port
), Name,Value
Name,Value
pair arguments.
Input Arguments
Master_Channel_Port
— Reference design port connected to IP core AXI4-Stream master interface
character vector
Reference design port connected to the IP core AXI4-Stream
master interface, specified as a character
vector. This port must be an AXI4-Stream slave
interface. If
master_channel_enable
is true
, you must specify
master_channel_port
.
Example: 'axi_dma_0/S_AXIS_S2MM'
Slave_Channel_Port
— Reference design port connected to IP core AXI4-Stream slave interface
character vector
Reference design port connected to the IP core AXI4-Stream
slave interface, specified as a character
vector. This port must be an AXI4-Stream master
interface. If
slave_channel_number
is
true
, you must specify
slave_channel_port
and
slave_channel_data_width
.
Example: 'axi_dma_0/M_AXIS_MM2S'
Tip
To add more than one AXI4-Stream interface to your reference design, call the
addAXI4StreamInterface
method multiple times depending on the
number of interfaces that you want to add. For each additional interface, specify a
unique InterfaceID
.
Name-Value Arguments
Specify optional pairs of arguments as
Name1=Value1,...,NameN=ValueN
, where Name
is
the argument name and Value
is the corresponding value.
Name-value arguments must appear after other arguments, but the order of the
pairs does not matter.
Before R2021a, use commas to separate each name and value, and enclose
Name
in quotes.
InterfaceID
— AXI4-Stream interface name
'AXI4-Stream' (default) | character vector
Name of the AXI4-Stream interface that you add to the reference design, specified as a character vector. To create multiple AXI4-Stream interfaces, make sure that you use unique names for each interface.
Example: 'InterfaceID','AXI4-Stream1'
MasterChannelEnable
— Master channel enable signal
'true' (default) | 'false'
Master channel enable signal, specified as
either true
or false
. By default,
MasterChannelEnable
is true
, so you must specify
master_channel_port
.
To use a reference design that has only a
Slave channel, set
MasterChannelEnable
to false
and do not specify the
master_channel_port
.
Example: 'MasterChannelEnable','false'
SlaveChannelEnable
— Slave channel enable
'true' (default) | 'false'
Slave channel enable signal, specified as
either true
or false
. By default,
SlaveChannelEnable
is true
, so you must specify
slave_channel_port
.
To use a reference design that has only a
Master channel, set
SlaveChannelEnable
to false
and do not specify the
slave_channel_port
.
Example: 'SlaveChannelEnable','false'
MasterChannelDataWidth
— Master channel data width
32 (default) | positive integer
Reference design master channel
TDATA
bit width, specified as a positive integer.
By default, the
master_channel_data_width
is 32
bits.
Example: 'MasterChannelDataWidth',32
SlaveChannelDataWidth
— Slave channel data width
32 (default) | positive integer
Reference design slave channel
TDATA
bit width, specified as a positive integer.
By default,
slave_channel_data_width
is 32
bits.
Example: 'SlaveChannelDataWidth',32
HasDMAConnection
— Indicate AXI4-Stream connection to Direct Memory Access (DMA)
false (default) | true | logical data type
Indicates if the AXI4-Stream interface is connected to the processor
through a DMA. Set this value to true
to enable
device tree generation for the IP core AXI4-Stream interfaces.
Example: 'HasDMAConnection','true'
DeviceTreeMasterChannelDMANode
— Reference to stream to memory-mapped (S2MM) DMA node in the device tree
" " (default) | string | character vector
Reference to the corresponding S2MM DMA node in the registered device
tree. Set the value to match the name of the corresponding S2MM DMA node
in the registered device tree. References to device tree nodes must
start with "&"
. To reference a node by its label,
specify "&"
before the label, such as
"&myLabel"
. To reference a node by its path,
specify the path inside "&{"
and
"}"
, such as
"&{/myNode/childNode}"
.
Set
MasterChannelEnable
to true
to specify this value.
Example: 'DeviceTreeMasterChannelDMANode','&axi4stream_s2mm'
DeviceTreeSlaveChannelDMANode
— Reference to memory-mapped to stream (MM2S) DMA node in the device tree
" " (default) | string | character vector
Reference to the corresponding MM2S DMA node in the registered device
tree. Set the value to match the name of the corresponding MM2S DMA node
in the registered device tree. References to device tree nodes must
start with "&"
. To reference a node by its label,
specify "&"
before the label, such as
"&myLabel"
. To reference a node by its path,
specify the path inside "&{"
and
"}"
, such as
"&{/myNode/childNode}"
.
Set
SlaveChannelEnable
to true
to specify this value.
Example: 'DeviceTreeSlaveChannelDMANode','&axi4stream_m2ss'
Version History
Introduced in R2020a
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