Real Reciprocal HDL Optimized

Compute reciprocal and generate optimized HDL code

Since R2021a

• 

Libraries:
Fixed-Point Designer HDL Support / Math Operations

Description

The Real Reciprocal HDL Optimized block computes 1/u, where u is a real scalar.

Examples

Implement Hardware-Efficient Real Divide HDL Optimized

How to use the Real Divide HDL Optimized block.

Open Live Script

Limitations

Data type override is not supported for the Real Reciprocal HDL Optimized block.

Ports

Input

u — Value to take reciprocal of

scalar | vector | matrix

Value to take the reciprocal of, specified as a real-valued scalar, vector, or matrix.

Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | fixed point

validIn — Whether input is valid

Boolean scalar

Whether input is valid, specified as a Boolean scalar. This control signal indicates when the data from the u input port is valid. When this value is 1 (true), the block captures the value at the u input port. When this value is 0 (false), the block ignores the input samples.

Data Types: Boolean

Output

y — Reciprocal

real scalar

Reciprocal, returned as a real scalar with the data type specified by the Output datatype parameter.

Data Types: single | double | fixed point

validOut — Whether output data is valid

Boolean scalar

Whether output data is valid, returned as a Boolean scalar. When the value of this control signal is 1 (true), the block has successfully computed the output at port y. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

Parameters

Output datatype — Data type of output

fixdt(1,18,10) (default) | single | fixdt(1,16,0) | <data type expression>

Data type of the output y, specified as fixdt(1,18,10), single, fixdt(1,16,0), or as a user-specified data type expression. The type can be specified directly, or expressed as a data type object, such as Simulink.NumericType.

Programmatic Use

Block Parameter: OutputType

Type: character vector

Values: 'fixdt(1,18,10)' | 'single' | 'fixdt(1,16,0)' | '<data type expression>'

Default: 'fixdt(1,18,10)'

Algorithms

Division by Zero Behavior

When the input u is zero and has a fixed-point data type, then the output y is equal to upperbound(Output datatype).

For floating-point inputs, the Real Divide HDL Optimized block follows IEEE^® Standard 754.

How to Interface with the Real Reciprocal HDL Optimized Block

Because of its fully pipelined nature, the Real Reciprocal HDL Optimized block is able to accept input data on any cycle, including consecutive clock cycles. To send input data to the block, the validIn signal must be true. When the block has finished the computation and is ready to send the output, it will change validOut to true for one clock cycle. For inputs set of consecutive cycles, validOut will also be set to true on consecutive cycles.

The latency is defined from the input to the corresponding output. For example in the figure below, from In1 to Out1, In2 to Out2, In3 to Out3, etc.

The latency depends on the input data type, as summarized in the table.

Input Type	Latency
fi	nextpow2(u.WordLength) + 1 + u.WordLength + 2 - issigned(u) + 7
Scaled double	u.WordLength + 2 - issigned(u) + 7
Floating point	7

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Slope-bias representation is not supported for fixed-point data types.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

Supports fixed-point data types only.

Version History

Introduced in R2021a