FIR Interpolator

Finite impulse response (FIR) interpolation filter

• Library:

• DSP HDL Toolbox / Filtering

• 

Description

The FIR Interpolator block implements a single-rate polyphase FIR interpolation filter that is optimized for HDL code generation. The block provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the block models architectural latency including pipeline registers and resource sharing.

The block accepts scalar or vector input and outputs a scalar or vector depending on the interpolation factor and the number of cycles between input samples. The block implements a polyphase decomposition with InterpolationFactor subfilters. Each subfilter can implement a serial architecture if there is regular spacing between input samples.

The block provides two filter structures. The direct form systolic architecture provides an implementation that makes efficient use of Intel^® and Xilinx^® DSP blocks. This architecture can be fully-parallel or serial. To use a serial architecture, the input samples must be spaced out with a regular number of invalid cycles between the valid samples. The direct form transposed architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.

All filter structures optimize hardware resources by sharing multipliers for symmetric or antisymmetric filters and by removing the multipliers for zero-valued coefficients such as in half-band filters and Hilbert transforms.

Ports

Input

data — Input data

real or complex scalar or vector

Input data, specified as a real or complex scalar or vector. The vector size must be less than or equal to 64. When the input data type is an integer type or a fixed-point type, the block uses fixed-point arithmetic for internal calculations.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: fixed point | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

valid — Indicates valid input data

scalar

Control signal that indicates if the input data is valid. When valid is 1 (true), the block captures the values from the input data port. When valid is 0 (false), the block ignores the values from the input data port.

Data Types: Boolean

reset — Clears internal states

scalar

Control signal that clears internal states. When reset is 1 (true), the block stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this port, on the Control Ports tab, select Enable reset input port.

Data Types: Boolean

Output

data — Interpolated output data

real or complex scalar or vector

Interpolated output data, returned as a real or complex scalar or vector. The vector size is InputSize * InterpolationFactor. When NumCycles is greater than InterpolationFactor, scalar output samples are spaced with floor(NumCycles/InterpolationFactor) invalid cycles, and the output valid signal indicates which samples are valid after interpolation.

When the input data type is a floating-point type, the output data inherits the data type of the input data. When the input data type is an integer type or a fixed-point type, the Output parameter on the Data Types tab controls the output data type.

Data Types: fixed point | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

valid — Indicates valid output data

scalar

Control signal that indicates if the data from the output data port is valid. When valid is 1 (true), the block returns valid data from the output data port. When valid is 0 (false), the values from the output data port are not valid.

Data Types: Boolean

ready — Indicates block is ready for new input data

scalar

Control signal that indicates that the block is ready for new input data sample on the next cycle. When ready is 1 (true), you can specify the data and valid inputs for the next time step. When ready is 0 (false), the block ignores any input data in the next time step.

Data Types: Boolean

Parameters

Main

Coefficients — FIR filter coefficients

fir1(35,0.4) (default) | real- or complex-valued vector

FIR filter coefficients, specified as a real- or complex-valued vector. You can specify the vector as a workspace variable or as a call to a filter design function. When the input data type is a floating-point type, the block casts the coefficients to the same data type as the input. When the input data type is an integer type or a fixed-point type, you can set the data type for the coefficients on the Data Types tab.

Example: firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0]) defines coefficients by using a linear-phase filter design function.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

Filter structure — HDL filter architecture

Direct form systolic (default) | Direct form transposed

Specify the HDL filter architecture as one of these structures:

• Direct form systolic — This architecture provides a parallel or partly serial filter implementation that makes efficient use of Intel and Xilinx DSP HDL blocks. For a partly serial implementation, specify a value greater than 1 for the Minimum number of cycles between valid input samples parameter. You cannot use frame-based input with the partly serial architecture.

• Direct form transposed — This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications.

The block implements a polyphase decomposition filter by using Discrete FIR Filter blocks. Each filter phase shares resources internally where coefficients and serial options allow. For architecture details, see FIR Filter Architectures for FPGAs and ASICs.

Interpolation factor — Interpolation factor

2 (default) | integer greater than two

Specify an integer interpolation factor greater than two. The output vector size is InputSize * InterpolationFactor. The output vector size must be less than 64 samples.

Minimum number of cycles between valid input samples — Serialization requirement for input timing

1 (default) | positive integer

Serialization requirement for input timing, specified as a positive integer. This parameter represents N, the minimum number of cycles between valid input samples. When you set Minimum number of cycles between valid input samples greater than the filter length, L, and the input and coefficients are both real, the filter uses Interpolation factor multipliers.

Because the block applies coefficient optimizations before serialization, the sharing factor of the final filter can be lower than the number of cycles that you specified.

Dependencies

To enable this parameter, set Filter structure to Direct form systolic.

You cannot use frame-based input with Minimum number of cycles between valid input samples greater than 1.

Data Types

Rounding mode — Rounding mode for type-casting the output

Floor (default) | Ceiling | Convergent | Nearest | Round | Zero

Rounding mode for type-casting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores this parameter. For more details, see Rounding Modes.

Saturate on integer overflow — Overflow handling for type-casting the output

off (default) | on

Overflow handling for type-casting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores this parameter. For more details, see Overflow Handling.

Coefficients — Data type of filter coefficients

Inherit: Same word length as input (default) | <data type expression>

The block casts the filter coefficients to this data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is floating point, the block ignores this parameter.

The recommended data type for this parameter is Inherit: Same word length as input.

The block returns a warning or error if either of these conditions occur.

• The coefficients data type does not have enough fractional length to represent the coefficients accurately.

• The coefficients data type is unsigned, and the coefficients include negative values.

Output — Data type of filter output

Inherit: Inherit via internal rule (default) | Inherit: Same word length as input | <data type expression>

The block casts the output of the filter to this data type. The quantization uses the settings of the Rounding mode and Overflow mode parameters. When the input data type is floating point, the block ignores this parameter.

The block increases the word length for full precision inside each filter tap and casts the final output to the specified type. The maximum final internal data type (WF) depends on the input data type (WI), the coefficient data type (WC), and the number of coefficients (L) and is given by

WF = WI + WC + ceil(log2(L)).

Because the coefficient values limit the potential growth, usually the actual full-precision internal word length is smaller than WF.

Control Ports

Enable reset input port — Option to enable reset input port

off (default) | on

Select this parameter to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Use HDL global reset — Option to connect data path registers to generated HDL global reset signal

off (default) | on

Select this parameter to connect the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink^®. When you clear this parameter, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Model Examples

Implement Digital Upconverter for FPGA

Design a digital upconverter (DUC) for LTE on FPGAs.

Open Script

Algorithms

The block implements a polyphase filter bank where the filter coefficients are decomposed into Interpolation factor subfilters. If the filter length is not divisible by the Interpolation factor parameter value, then the block zero-pads the coefficients.

The diagram shows the polyphase filter bank with scalar input and the Interpolation factor parameter set to four. Each subfilter contributes one sample to the output vector. When you set Minimum number of cycles between valid input samples greater than 1, the block passes the NumCycles value to the FIR filters for each phase, and each FIR filter implements a partly-serial architectures.

The next diagram shows the polyphase filter bank for an input vector of two values and the Interpolation factor parameter set to four. Each of the four subfilters generates two samples of the output vector.

Each subfilter is implemented with a Discrete FIR Filter block. For architecture details, see FIR Filter Architectures for FPGAs and ASICs.

Performance

This table shows the post-synthesis resource utilization for the HDL code generated for the default FIR interpolation filter using scalar input, an interpolation factor of two, 16-bit input, and 16-bit coefficients. The synthesis targets a Xilinx ZC-706 (XC7Z045ffg900-2) FPGA. The Global HDL reset type parameter is Synchronous, and the Minimize clock enables parameter is selected. The reset port is disabled, so only the control path registers are connected to the generated global HDL reset.

Resource	Uses
LUT	18
FF	353
BRAM	0
Xilinx LogiCORE DSP48	72

After place and route, the maximum clock frequency of the design is 455 MHz.

For the same filter configuration but with a four-element input vector, the filter uses these resources.

Resource	Uses
LUT	2080
FF	6416
BRAM	0
Xilinx LogiCORE DSP48	288

After place and route, the maximum clock frequency of the design is 385 MHz.

For a design with scalar input, an interpolation factor of four, and Minimum number of cycles between valid input samples set to four, the filter uses these resources. You can see the effect of sharing filter resources over the invalid cycles between input samples.

Resource	Uses
LUT	1100
FF	2258
BRAM	0
Xilinx LogiCORE DSP48	24

After place and route, the maximum clock frequency of the design is 540 MHz.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2022a