Stateflow

Model and simulate decision logic using state machines and flow charts

Stateflow provides a graphical language that includes state transition diagrams, flow charts, state transition tables, and truth tables. You can use Stateflow to describe how MATLAB algorithms and Simulink models react to input signals, events, and time-based conditions.

Stateflow enables you to design and develop supervisory control, task scheduling, fault management, communication protocols, user interfaces, and hybrid systems.

With Stateflow, you model combinatorial and sequential decision logic that can be simulated as a block within a Simulink model or executed as an object in MATLAB. Graphical animation enables you to analyze and debug your logic while it is executing. Edit-time and run-time checks ensure design consistency and completeness before implementation.

Get Started:

Design Control Logic
Execute and Debug Charts
Develop Reusable Logic for MATLAB Applications
Schedule Simulink Algorithms
Validate Designs and Generate Code

What Is Stateflow?

Free Interactive Course

Stateflow Onramp

Get started

Design Control Logic

Model system logic using state machines, flow charts, and truth tables.

Designing State Machines Graphically

Build state machines graphically by drawing states and junctions connected by transitions. You can also create functions using flow chart notation, Simulink subsystems, MATLAB code, and truth tables.

Represent Operating Modes by Using States

Simulink Subsystems as States

Reuse MATLAB Code by Defining MATLAB Functions

Getting Started with Stateflow Video (12:48)

Stateflow diagram defining the logic for a boiler temperature control system. The diagram uses graphical functions (right side) to implement utility algorithms called by the heater system (left side).

Designing Flow Charts

Create flow charts by drawing transitions that are connected at junctions. The Pattern Wizard lets you create commonly used logic flow patterns. You can use flow charts to design logic for transitioning between states.

Flow Charts in Stateflow

Create Flow Charts by Using Pattern Wizard

Represent combinatorial logic such as decision trees and iterative loops graphically with flow charts.

Designing Logic with Tables

Truth tables in Stateflow let you model logic in Simulink when the output depends purely on the current input. State transition tables provide a structured environment for modeling state machines in Simulink.

Reuse Combinatorial Logic by Defining Truth Tables

State Transition Tables in Stateflow

State Transition Tables - Video (4:53)

Truth table implementing the logic for selecting a valid sensor reading in a fault-detection algorithm.

Execute and Debug Charts

Visualize the behavior of your system for analysis and debugging.

Executing Stateflow Charts

Visualize system behavior using state diagram animations to highlight active states and transitions in your charts.

Execution of a Stateflow Chart

Types of Chart Execution

Understanding Complex Logic with Stateflow

Debugging Stateflow Charts

Stateflow debugging capabilities let you step through chart execution in detail. You can set breakpoints, monitor data values, and step through different functions in your state diagrams.

Set Breakpoints to Debug Charts

Detect Modeling Errors During Edit Time

Analyzing and Debugging Logic with Stateflow Video (4:00)

Simulation data visualization options in Stateflow. Top left: Simulink Data Inspector for comparing specific signals; bottom left: custom MATLAB interface for analyzing data; right: Simulink Signal Selector for comparing specific states.

Develop Reusable Logic for MATLAB Applications

Use Stateflow chart objects to develop reusable logic for MATLAB applications. Design state machine and timing logic for a wide range of applications, including test and measurement, autonomous systems, signal processing, and communications.

Reusable Chart Objects

Create standalone Stateflow charts that use the full capabilities of the MATLAB language in state and transition actions. Use these charts as MATLAB objects in your applications that require state machine and timing logic.

Create Stateflow Charts for Execution as MATLAB Objects

Execute and Unit Test Stateflow Chart Objects

Debug a Standalone Stateflow Chart

State Machine and Timing Logic

Accelerate the development of MATLAB applications by using Stateflow to graphically design state machine and timing logic that would be difficult to implement textually.

Design Human-Machine Interface Logic by Using Stateflow Charts

Model a Communications Protocol by Using Chart Objects

Analog Trigger App by Using Stateflow Charts

Using Stateflow to Provide the Logic for a MATLAB App

Deploying Stateflow Applications

Create MATLAB applications that include Stateflow chart objects and share them without requiring Stateflow.

Share MATLAB applications that include Stateflow charts without needing a Stateflow license.

Share MATLAB applications that include Stateflow chart objects with users who do not have Stateflow.

Schedule Simulink Algorithms

Schedule algorithms modeled in Simulink.

Periodic and Continuous Scheduling

You can model conditional, event-based, and time-based logic in Stateflow to invoke Simulink algorithms in a periodic or continuous manner. Orchestrate the execution of components to simulate the scheduling of your real-time environment.

Transition Between Operating Modes

Continuous-Time Modeling in Stateflow

Synchronize Model Components by Broadcasting Events

You can model logic in Stateflow to call Simulink and MATLAB algorithms in a periodic or continuous manner.

Temporal Operators

Use event-based and time-based operators (such as after and duration) to specify state-transition logic based on event counts, elapsed time, and denoised signals without having to create and maintain your own timers and counters.

Control Chart Execution by Using Temporal Logic

Control Oscillations Using the Duration Operator

Temporal Logic Operators

Validate Designs and Generate Code

Validate your design against requirements and generate code for implementation on your embedded system.

Validating Designs

Use Stateflow with other Simulink products to validate your design against requirements.

Link requirements directly to Stateflow objects using drag and drop with Requirements Toolbox.
Check that your state diagrams comply with standards using Simulink Check.
Collect model and generated code coverage metrics with Simulink Coverage.
Detect design errors and generate test vectors using Simulink Design Verifier.
Develop, manage, and execute simulation-based tests with Simulink Test.

Highlight Active Logic using Model Slicer.

Generating Code

Generate code for implementation of your Stateflow logic on embedded systems.

Generate C and C++ code from Simulink and Stateflow models using Simulink Coder.
Generate VHDL and Verilog code for FPGA and ASIC designs with HDL Coder.
Generate IEC 61131-3 Structured Text for PLCs and PACs using Simulink PLC Coder.