Statistics
2 Questions
0 Answers
RANK
145 892
of 293 504
REPUTATION
0
CONTRIBUTIONS
2 Questions
0 Answers
ANSWER ACCEPTANCE
50.0%
VOTES RECEIVED
0
RANK
of 20 034
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 148 733
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
Feeds
Question
[HDL Coder] How to keep subsystems port names when applying input/output pipelining
Hello, I am currently developping a control algorithm which will be implemented inside a Xilinx Spartan6 FPGA. I generate the...
mer än 9 år ago | 1 answer | 0
1
answerQuestion
HDL Coder Workflow Advisor timing analysis
Hello! I am currently working on a project for which my task is to develop a control algorithm for a power converter. This alg...
mer än 9 år ago | 1 answer | 0