Julien

Last seen: 4 månader ago | Active since 2024

Followers: 0 Following: 0

Statistics

Feeds

Question

Can you use switches as inputs in a design tested with FPGA-in-the-Loop simulation? (on a Zedboard)
Hello, I am currently testing the abilities of the HDL Verifier Toolbox. I tried the FIL simulation with a design and it works....

4 månader ago | 1 answer | 0

1

answer

Question

HDL Verifier "Verify HDL Module with MATLAB Test Bench" Tutorial: Cannot find example code from Tutorial.
Hello, I tried to do the "Verify HDL Module with MATLAB Test Bench" Tutorial for the HDL Verifier add-on. In the "Set up Tutoria...

5 månader ago | 1 answer | 0

1

answer