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Question
Buffer and enable in simulink
Put buffer block and enable in a subsystem. Suppose step = 1, buffersize = 9 and enable signal is effective in 1.5s ~ 9.5s. So I...
mer än 14 år ago | 0 answers | 0
0
answersQuestion
How to build a simulink model which can generate HDL coder to resize images or videos?
I want to resize images or videos by FPGA. I only know the resize block but it cannot generate HDL code. Anybody can teach me or...
mer än 14 år ago | 4 answers | 0
4
answersQuestion
The demo of hdlcoder_sobel_serial_eml.mdl
In the sobel_edge_eml of sobel_edge_hardware of hdlcoder_sobel_serial_eml.mdl, there are three inputs u, thresh and C in the fun...
mer än 14 år ago | 1 answer | 0
