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Question
AXI4 Master Read SDRAM
I'm using a Cyclone V SoC and in my reference design I have a FPGA to HPS SDRAM Interface enabled under the HPS. I'm expecting s...
26 dagar ago | 1 answer | 0
1
answerQuestion
Unable to fit HDL coder design into FPGA
I'm having trouble getting the HDL IP core generated by the HDL coder to fit in the FPGA I'm targeting (Cyclone V). I'm using th...
ungefär 2 månader ago | 1 answer | 0
1
answerQuestion
PMLSM Controller Over Active
I started with the three phase PMLSM example: https://www.mathworks.com/help/sps/ug/three-phase-pmlsm-drive.html . I modified th...
3 månader ago | 1 answer | 0
1
answerQuestion
Specify the Location of custom IP cores in HDL Coder
I was following along with the instructions here: https://www.mathworks.com/help/hdlcoder/ug/define-and-add-ip-respository-to-cu...
7 månader ago | 1 answer | 0
1
answerQuestion
HDL Coder with Custom IP Core
I was trying to add a custom IP core to my reference design and now when I run HDL workflow advisor using the hdl_led_blinking s...
7 månader ago | 1 answer | 0
1
answerQuestion
Cannot find header file in Simulink Coder
I'm using the C Function block in Simulink to import custom C code into my model. Most of the standard C libraries I include Sim...
8 månader ago | 2 answers | 0
2
answersQuestion
Read AXI4 address locations from Simulink
How can I read a particular address location from the AXI4 interface within Simulink HDL coder? For example, if I have a referen...
8 månader ago | 1 answer | 0
1
answerQuestion
Build Linux Image for HDL Coder
I'm trying to follow along with the documentation here: https://www.mathworks.com/help/hdlcoder/ug/xilinx-zynq-linux-image-for-c...
8 månader ago | 0 answers | 0
0
answersQuestion
Use Conduit Interface in HDL Coder
If I have a reference design that includes an IP core with a Conduit interface, how can I reference these signals in HDL coder? ...
8 månader ago | 0 answers | 0
0
answersQuestion
HDL Coder Support Package for Intel FPGA and SoC Devices Setup
I am trying to go through the hardware setup for the HDL Coder Support Package for Intel FPGA and SoC Devices. I get to the step...
9 månader ago | 0 answers | 0
0
answersQuestion
Specify clock pins in HDL Reference Design
I was reading over how to register a custom reference design: https://www.mathworks.com/help/hdlcoder/ug/register-a-custom-refer...
9 månader ago | 1 answer | 0
