Simulation problems of FPGA-in-th​e-loop(sim​ulink)

Hi, I'm using FPGA-in-the-loop (simulink) to verify my design, as shown in figure1. I generated the expected data (*.dat) from HDL Coder's "Verify with HDL test bench" step. I read the dat file in hex format in matlab [fscanf(fid,'%x');] and load it into simulink using 'from workspace' block, then change the data type from 'double' to fix point. Meanwhile, I set the output signal attributes in the generated FIL model to 'ufix' model (figure2). In this way, I can compare them completely in fix point level. However, I found that data returned by JTAG is inconsistent with the expected data, as shown in figure3. The simulation result shows that sometimes when 'zero' is expected, the output data from DUT seems like a negative number with a small absolute value (in 2's complement format). How to explain this problem or how to fix it?

Figure 1:

Figure 2:

Figure 3:

Answer 1

[Mukesh Chugh]

Hi,

First, if you haven't verified already please verify the HDL Code with an HDL Simulator and make sure it passes with the same stimulus. You may use the HDL Cosimulation feature of HDL Verifier. If that passes, your FIL verification should pass as well.

In case you are using the HDL Coder for generating code and trying to use FPGA-in-the-loop, I suggest using an automated workflow that generates the test-bench model with FIL Block with all necessary data-type conversions taken care of. Please have a look at this example for reference.

In case you are using Simulink FIL to verify a hand-written HDL code, I suggest using filWizard to create a FIL block, which helps with data types of the input/output ports in Simulink.

Thanks,