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Hardware platform for "Stereo Disparity using Semi-Global Block Matching" example

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Hi, I tried the example "Stereo Disparity using Semi-Global Block Matching" in Simulink and generated the HDL for IP. However, when I tried to test it on the actual hardware (Zedboard SOC) with image streaming using VDMA IP, the output is totally not recognizable. It seems that the control signals generated by the IP at the output are not generated properly as required by the VDMA IP. For instance, it totally discards the front and back porch. In simulation on Simulink, these signals are probably not required and thus the output is as expected. Any leads?? Thanks

Answers (1)

Bharathi Yogaraj
Bharathi Yogaraj on 27 Apr 2021
Currently, output frame is reconstructed only based on valid signal. The algorithm does not consider back & front porch during processing. There are two options that can be explored as under.
  1. Pixel Stream Aligner block can be used to get the reference and generate the control bus for output as required.
  2. VDMA IP has an optional data re-alignment engine (DRE) feature that can be enabled to realign the frame to get the required output format.




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