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How to generate HDL code for fractional sample rate converter in simulink?

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I have a simulink block as follows
I want to generate hdl code for the whole model. Gb, Ib, Kb and Pb are my filters and I am designing fractional sample rate converter. But it only generates hdl code for filter not for up-sampling and down-sampling process. I want to do that because my filter length is 391 and it is very hard to write testbench manually for such a big filter. Please help!
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Himadri Debnath
Himadri Debnath on 22 Mar 2021
It only generates hdl code for Gb, Ib, Kb and Pb. These are amy filters. I want to generate verilog code for whole system including upsampling and downsampling process and thus testbench. how to do that?

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Accepted Answer

Kiran Felix Robert
Kiran Felix Robert on 22 Mar 2021
Edited: Kiran Felix Robert on 22 Mar 2021
Hi Himadri,
As we see from the upsample and downsample block documentation, they support HDL Code generation. Try Code generation after creating a subsystem with all the blocks, for which you will generate the HDL Code.
In your case, create a subsystem with all the upsample and downsample blocks and the filters. That is, let the sine wave be the input and scope be the output to the subsystem, and generate the code for the new subsystem, This will generate the HDL Code for all your blocks. Refer the Generate HDL Code from Simulink Model.

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