How can I input expected output values for a signal to simulink design verifier and generate tests with it?

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Hi,
I want to get a test case which gives a specific value for an output signal. In other words I want to find the combination of the input signal values which gives me my desired value for a specific output signal.
As far as I understand from the documentation, it is possible to do it with simulink design verifier test generation function. I read, it is possible with "include expected output value option". However I can`t find how to input expected results for the output signal. I would be very happy if someone can help me with this issue. Any information or example would be highly appreciated!
Thank you very much in advance!

Answers (1)

Pat Canny
Pat Canny on 12 Mar 2020
Edited: Pat Canny on 12 Mar 2020
Hi Xinkun,
Thank you for your question.
I recommend you use a Test Objective block, which you can use to define a desired value for any signal in your model. You can also use the Test Condition block to constrain other signal values. Simulink Design Verifier will try to generate any test that achieves the objective of reaching the value defined within the Test Objective, and will constrain other signals accordingly based on the Test Conditions.
Try the following example for Test Objective blocks:
sldvdemo_debounce_testobjblks
A Test Condition block can also be used to constrain the rate of change of a signal, which is commonly required. This can be achieved using standard Simulink blocks, such as in this simple example:
The "Expected Output" option will actually create a cell array of vectors containing the output values of the model outputs after the tests are generated. This is a bit confusing, and I will take this feedback to our Documentation team.
  2 Comments
Xinkun Wu
Xinkun Wu on 13 Mar 2020
Hi,
thank you very much for your answer. I will try using test objective block.
I have one more question. I have a very complex model and it has also parameters in addition to input signals.Therefore simulink design verifier should change the parameter values as well in order to get desired output.
Does sldv change parameters in addition to input signals? If yes,is it enough, if I go to configuration then active enable parameter configuration --> Use parameter table --> Find in model?
Thank you very much in advance
Pat Canny
Pat Canny on 18 Mar 2020
Hi Xinkun,
Yes, the parameter table should work for your use case. The parameter should be defined as a Simulink.Parameter, otherwise it might not be found when you use "Find in Model".
Thanks.
- Pat

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