How can I figure out how many delay units do I need in one part of Simulink HDL design?

Hi,

Recently, I am interested in debuging your ZYNQ hwswcodesign model. The figure below is one part of Rx Data decoding block. My question is how do you know the exact delay numbers in this design?

Thanks in advance.

Answer 1

[Bharath Venkataraman]

One of the ways to do this is by logging the input and output signals to the Logic Analyzer. You can set your cursors on the input and output signals and observe the altency. This only works if your design has a fixed latency.