"Error: Synthesis failed", "HDL compilation failed"

Hello,

I am having trouble generating an FPGA-in-the-loop (FIL) test bench.

When compiling, it gets as far as "wait_on_run synth_1", which then fails, leading to compilation failure.

The code is a simple adder function that has compiled before,

function x=adder(a,b)
x=a+b;
end

which is called by the test bench with a test.m containing

f=adder(3,0.1);
f=adder(2,0.4);

Compilation has compiled successfully in the past, just the FIL aspect seems to fail.

• I am attempting to compile it for the Xilinx Zynq ZC706 evaluation kit board (FIL compatible)
• The FPGA is currently being connected through JTAG as opposed to PICe
• I have set the correct directory for the Xilinx vivado binary, which is up to date
• This error occurs even with the FPGA turned off
• I am using the required packages such as HDL Coder, HDL verifier, Fixed-Point Designer, MATLAB Coder.

I have experienced a similar problem in the "Validate FPGA Board menu, though the program generation fails during the implementation phase instead of synthesis.

Does anyone have any advice or insight to get it to compile successfully?

Thanks.

Answer 1

[andrew kurtz]

I have solved the problem:

Vivado and MATLAB were missing a license file needed to synthesize and implement the program.

[xioabo li]

Hello,

Could you please give me more details about the license file?

Thanks