How can i measure execution time or clock cycles utilized by a bloc simulink which will be run on FPGA" zedboard"?

I need to measure or estimate the number of clock cycle utilized by a bloc simulink runing on FPGA. I use HDL workflow to implement my bloc system on zedboard.

Answer 1

[Bharath Venkataraman]

If you have a valid in and valid out signals, or a similar protocol, you can plot these signals into the Logic Analyzer and put cursors at the two points of interest and see how many cycles it takes.

You can also pass these input and output valid signals to a counter and use them to start and stop the counter.

[mouna riabi]

Please can you give me an example with Logic Analyzer to measure number of cycles between output and input because i found only examples which use the waveforms and observe signals. Or if you can explain me more. thank you