Ethernet connexion issue with FIL programmation

Hi!

I'm working on an Altera Stratix IV board with a EP4SGX530KH40C2 device. At the end of the FPGA validation in filWizard with an Ethernet connection, I can see the Rx led lighting up but the Tx led stay not lighting and the ping is failed. I have to notice that the quartus programmer is still opened to keep the Ethernet connection available. Is there someone who already had this issue ?

Thanks for your help.

Answer 1

[Tao Jia]

Can you manually ping the board? If that works, you can probably ignore the auto validation error. You should be able to run FPGA-in-the-Loop feature normally by just waiting for the programmer to finish before starting the simulation.

[Maxence Voisin]

Yes, that's what I did.

Thanks for your reply.

Answer 2

[Tao Jia]

I assume that you are using the SGMII mode to connect. In that case, the answer to this question might be helpful:

https://www.mathworks.com/matlabcentral/answers/337646-filwizard-error-during-validation-of-altera-stratix-iv-gx-230-fpga-development-kit

Basically, you'll need to make sure that the quartus programming is opened and running. Also, what is the PHY chip that you are using? There might be some compatibility issue.

[Maxence Voisin]

Thanks for your reply.

The issue is partially fixed by setting the SW2 switch to the factory mode (position 0). With this configuration I can have an Ethernet connection with the binary generated with the VHDL that I created.

When I try to validate the Ethernet connection in filWizad (with the same board) the software can't dialog with the board via Ethernet connection, it seems to be filWizard is checking the packets whereas Quartus programmer has not finished to process.