HDL workflow advisor: how to make use of 'external port' in the target platform interfaces

I am modifying the built in hdlcoder_led_blinking so that it also can read input from an external IO pin. is there any reference on how to do it? I select 'external port' in the workflow advisor but i not sure what to set for bit range/address/fpga pin. i am trying to connect to PMOD1.0 (connector bay J63) menntioned in page 49 of https://www.xilinx.com/support/documentation/boards_and_kits/zc702_zvik/ug850-zc702-eval-bd.pdf

somewhere in the documention it is mentioned if i want to do external port i need add fpga pin assignment constraints in Vivado. How to do so?

[Nadereh Rooein]

Please see the doc page below:

https://www.mathworks.com/help/releases/R2019a/supportpkg/xilinxzynq7000/ug/generate-a-custom-ip-core-for-zynq-7000-platform-from-simulink.html

Answer 1

[Shivang Menon]

To connect to FPGA external IO pins, for Bit Range / Address / FPGA Pin, enter a cell array of pin names. If you do not enter pin names in a cell array format, the external ports are left unconnected in the embedded system tool project. For example, based on the pdf you provided j63 connector bay corresponds to pin E15, D15, W17 and W5. So, you can try setting external port as ufix4 and entering a cell {'E15', 'D15', 'W17', 'W5'}. Refer to step 4 in the following link :

Generate IP Core from Zynq 7000 platform from simulink

Hope this helps!