Getting Started with Hardware-Software Codesign Workflow for Xilinx Zynq Platform - BUG

Hi, I was doing the example on Matlab for Xilinx Zynq Example and there is a bug during the generation of the bitstream file. See command windows prompt:

WARNING: [Synth 8-350] instance 'inst' of module 'processing_system7_v5_4_processing_system7' requires 686 connections, but only 673 given [c:/Users/JeanJacques/Documents/MATLAB/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/ip/system_top_processing_system7_0_0/synth/system_top_processing_system7_0_0.v:305] INFO: [Synth 8-256] done synthesizing module 'system_top_processing_system7_0_0' (39#1) [c:/Users/JeanJacques/Documents/MATLAB/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/ip/system_top_processing_system7_0_0/synth/system_top_processing_system7_0_0.v:57] INFO: [Synth 8-256] done synthesizing module 'system_top' (40#1) [C:/Users/JeanJacques/Documents/MATLAB/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/hdl/system_top.vhd:608] INFO: [Synth 8-256] done synthesizing module 'system_top_wrapper' (41#1) [C:/Users/JeanJacques/Documents/MATLAB/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/hdl/system_top_wrapper.vhd:41] TclStackFree: incorrect freePtr. Call out of sequence? [Sun May 01 22:22:24 2016] synth_1 finished wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:01:31 . Memory (MB): peak = 361.410 ; gain = 0.000 # launch_runs impl_1 -to_step write_bitstream ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1'. The following runs need to be reset first synth_1 while executing "launch_runs impl_1 -to_step write_bitstream" (file "vivado_build.tcl" line 7) INFO: [Common 17-206] Exiting Vivado at Sun May 01 22:22:24 2016...

See screenshot:

Answer 1

[Tim McBrayer]

This error message is coming from Xilinx Vivado, not from MATLAB or HDL Coder. You should be able to load the project file the HDL Coder has created directly into Vivado and investigate further.