Assistance Required: Warning during Simscape HDL Workflow Advisor Conversion Process

Dear All,

I am writing to request assistance with converting my Simscape Electrical model to an implementation model using the Simscape HDL Workflow Advisor.

The first two steps of the process completed successfully; however, I encountered a warning during the final step (please see the attached screenshot), even though the simulation results are pretty much the same.

Furthermore, despite selecting the "Generate validation logic for the implementation model" option, no validation logic files were created. I also tested the process using other examples, such as the Boost Converter Model available at the following link, and did not encounter any issues: https://kr.mathworks.com/help/hdlcoder/ug/get-started-with-simscape-hardware-in-the-loop-workflow.html#mw_fb1c1ee8-3029-4c01-8028-e75e30024206

Could you please advise on the cause of this warning and suggest how I might resolve the issue? For your reference, I have attached the Simscape model file (DCDCLLCConverter_original.slx) used in my conversion.

Thank you for your assistance.

Best regards,

Answer 1

[Aabha]

Hi @Minkwang Lee,

I tried running the Simscape HDL Workflow Advisor on your model and was able to reproduce the issue. To fix this issue, you will need to run the command “hdlsetup” on your model. This function sets up the parameters of the specified model to common default values for HDL code generation. You can run the following command in the MATLAB command window:

hdlsetup('DCDCLLCConverter_original')

After the model parameters are setup, you can run the Simscape HDL Workflow Advisor to generate HDL code from your model, using the following command.

sschdladvisor('DCDCLLCConverter_original')

Please note that, you may get a warning regarding the sample time, since the sample time of the solver in your model is set to “1e-7” which might not be achievable on the FPGA clock frequency. You can either run FPGA synthesis to determine if the required clock frequency is achievable, or lower the required sample time of your model. You can reduce the sample time using the “Solver Configuration” block parameters. Setting the sample time to “1e-5” worked for me. Also, if you now select the “Generate validation logic for the implementation model”, and then click on “Run This Task”, the state space validation files will be generated successfully.

I hope this works for you.