Ultra RAM on True Dual Port RAM

HI,

I try to design True Dual Port RAM on Ultra RAM. I use block primitive True Dual Port RAM in 2024a and set RAMDirective 'ultra'. Generated code has this attribute. But when implemen step in Vivado, i have info, that attribute ultra is ignored because invalid write mode. And after implementing my RAM design by block RAM, but i need based on Ultra RAM

Please, give advice about this problem

Answer 1

[Kiran Kintali]

Please do attach your sample model as a test case.

This is a known issue and HDL Coder R&D team have reported the issue to Vivado community. See the discussion here https://adaptivesupport.amd.com/s/question/0D74U000007ua50SAA/detail?language=en_US

See the attached model RAM based FIR filter.

Here are the code generation settings

%FPGA DUT Subsystem: 'hdlcoderfirram/FIR_RAM'

>> hdlsaveparams('hdlcoderfirram/FIR_RAM')

hdlset_param('hdlcoderfirram', 'HDLGenerateWebview', 'on');
hdlset_param('hdlcoderfirram', 'HDLSubsystem', 'hdlcoderfirram/FIR_RAM');
hdlset_param('hdlcoderfirram', 'InitializeBlockRAM', 'off');
hdlset_param('hdlcoderfirram', 'NoResetInitializationMode', 'None');
hdlset_param('hdlcoderfirram', 'ProjectFolder', 'hdl_prj');
hdlset_param('hdlcoderfirram', 'ResetType', 'Synchronous');
hdlset_param('hdlcoderfirram', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('hdlcoderfirram', 'SynthesisToolChipFamily', 'Virtex UltraScale+');
hdlset_param('hdlcoderfirram', 'SynthesisToolDeviceName', 'xcvu9p-flga2104-2L-e');
hdlset_param('hdlcoderfirram', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('hdlcoderfirram', 'TargetFrequency', 400);
hdlset_param('hdlcoderfirram', 'TargetLanguage', 'Verilog');
hdlset_param('hdlcoderfirram', 'Traceability', 'on');

hdlset_param('hdlcoderfirram/FIR_RAM/Dual Port RAM', 'RAMDirective', 'ultra');

hdlset_param('hdlcoderfirram/FIR_RAM/Dual Port RAM System', 'RAMDirective', 'ultra');

Generate HDL Code with the settings

>> makehdl('hdlcoderfirram/FIR_RAM')
### Working on the model hdlcoderfirram
### Generating HDL for hdlcoderfirram/FIR_RAM
### Using the config set for model hdlcoderfirram for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoderfirram'.
### Begin compilation of the model 'hdlcoderfirram'...
### Begin compilation of the model 'hdlcoderfirram'...
### Working on the model 'hdlcoderfirram'...
### Working on... GenerateModel
### Begin model generation 'gm_hdlcoderfirram'...
### Copying DUT to the generated model....
### Model generation complete.
### Generated model saved at hdl_prj\hdlsrc\hdlcoderfirram\gm_hdlcoderfirram.slx
### Begin Verilog Code Generation for 'hdlcoderfirram'.
### Begin Verilog Code Generation for 'FIR_RAM_tc'.
### Working on FIR_RAM_tc as hdl_prj\hdlsrc\hdlcoderfirram\FIR_RAM_tc.v.
### Code Generation for 'FIR_RAM_tc' completed.
### Working on... Traceability
### Working on... HDLGenerateWebview
### Working on hdlcoderfirram/FIR_RAM/FIR_Addr as hdl_prj\hdlsrc\hdlcoderfirram\FIR_Addr.v.
### Working on hdlcoderfirram/FIR_RAM/DualPortRAM_generic as hdl_prj\hdlsrc\hdlcoderfirram\DualPortRAM_generic.v.
### Working on hdlcoderfirram/FIR_RAM/DualPortRAM_generic as hdl_prj\hdlsrc\hdlcoderfirram\DualPortRAM_generic_block.v.
### Working on hdlcoderfirram/FIR_RAM as hdl_prj\hdlsrc\hdlcoderfirram\FIR_RAM.v.
### Code Generation for 'hdlcoderfirram' completed.
### Generating HTML files for code generation report at index.html
### Creating HDL Code Generation Check Report FIR_RAM_report.html
### HDL check for 'hdlcoderfirram' complete with 0 errors, 5 warnings, and 0 messages.
### HDL code generation complete.
>> 

Look at the generated code files

>> cd hdl_prj\hdlsrc\hdlcoderfirram\
>> !grep ultra *.*
DualPortRAM_generic.v:  (* ram_style  = "ultra" *)   reg[DataWidth - 1:0] ram [2**AddrWidth - 1:0];
DualPortRAM_generic_block.v:  (* ram_style  = "ultra" *)   reg[DataWidth - 1:0] ram [2**AddrWidth - 1:0];
>> 

After applying the RAM_STYLE attribute as “ultra” the Vivado Synthesis does not infer URAMs. The following warning can be seen in Vivado Synthesis:

The ram_style = "ultra" set on RAM "Subsystem/u_Dual_Port_RAM/ram_reg" is ignored because invalid write mode

HDL Coder team is working with AMD to address the coding style. Please reach out to tech support for additional help.

[Nick]

Thanks for your fast and great answer! Attach my reference file. But i don't think you will surprised - because my take is very simple. Mmm, use 2024a with vivado 2022.1, but this version doesnt complitly at all. If i up version vivado, can it change something or need wait next bug fix?

If write hdl code for dual port RAM with template which vivado use for implement for URAM and use 'importhdl' in Matlab? Is this posible or i cant do this because 'importhdl' has restriction for this type RAM primitive?

[Kiran Kintali]

This is a bit of clunky workaround, but I can see it may help in the short term.

https://www.mathworks.com/help/hdlcoder/ug/integrate-custom-hdl-code-using-docblock.html

Move the RAM block in your Simulink model into a subsystem, right click on the Subsystem and mark it a blackbox in the HDL Block Properties. Now add a doc block with the expected HDL Text from Vivado (see the link above) for the ultraRAM in it and regenerate HDL code with HDL Coder. This will ensure HDL Coder uses your supplied code and not auto-generated template for the RAM.

This is a temporary workaround until HDL Coder dev team can fix the style of the generated code to match the Vivado requirements for Ultra RAM inference.

We will post here an update when the patch is available for R2024a and R2024b releases.

[Nick]

Great, the best, thanks a lot!

[Dan]

Hello, would you be able to provide an update on this as we are running in to the same issue.