Can't understand individual VHDL files generated.
19 views (last 30 days)
Show older comments
Jaykishan Solanki
on 5 Jul 2024 at 5:29
I have generated hdl code from a simulink model, but it has created many files. I don't have any prior experience with VHDL and can't understand what is each file doing. Is there any way to know what the individual VHDL files are doing?
0 Comments
Accepted Answer
Aditya
on 5 Jul 2024 at 6:10
Hi Jaykishan,
Please refer to this MATLAB documentation to understand the generated HDL code:
This documentation explains the file structure and how you can understand different parts, as well as the mapping between Simulink components and the generated code.
0 Comments
More Answers (0)
See Also
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!