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PLL phase-locked frequency failure

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xin
xin on 25 May 2024 at 16:21
Answered: UDAYA PEDDIRAJU on 6 Jun 2024 at 6:23
I used the RTU box 204 to build the PLL phase-locked loop, in order to eliminate the algebraic loop, in the phase wt and dq transformation between the feedback loop added unit delay module, the interrupt frequency is 10kHz, but the frequency of the phase-locked slowly increased from 50Hz to more than 70Hz; If the unit delay module is removed it indicates that there is an algebraic loop code generation failure. The PI parameters of the phase-locked loop have been changed, but the frequency keeps increasing. Where should I troubleshoot the problem?

Answers (1)

UDAYA PEDDIRAJU
UDAYA PEDDIRAJU on 6 Jun 2024 at 6:23
Hi Xin,
Your PLL drift using RTU box 204 likely stems from the unit delay or PI parameters.
  • Unit Delay: Ensure the unit delay is placed correctly to break algebraic loops without unintended delays.
  • PI Parameters: Start with a low P gain and adjust the I gain for settling time. High P gain can cause drift.
  • Review Configuration: Verify RTU box settings match your PLL application (reference frequency, scaling).
  • Hardware Check: Look for loose connections, component tolerances, or noise issues.
Consider monitoring the phase error signal for troubleshooting.

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