Can you use switches as inputs in a design tested with FPGA-in-the-Loop simulation? (on a Zedboard)

Hello,

I am currently testing the abilities of the HDL Verifier Toolbox. I tried the FIL simulation with a design and it works. But the design isn't using external peripherals of my Zedboard (which I'm working on). I asked myself if it is even possible to integrate external peripherals in a FIL simulation? Like using a Switch on the Zedboard to trigger an output of my DUT.

Best regards,

Julien

Answer 1

[Tom Richter]

Hi Julien,

FIL is just for testing an algorithm independently of any peripherals. What you like to do is FPGA Prototyping. Starting with an IP Core Generation Workflow, you can use one of the supported boards and reference designs that come with the HDL Coder support package. In the target interface settings, you can then select some of the peripherals such as switches, LEDs, etc. Other signals can be mapped to AXI4 memory mapped or streaming interfaces that can later be written to or read from. Here is a simple documentation example: “Getting Started with Targeting Xilinx Zynq Platform”.

For the Streaming Interface get started with “Deploy Model with AXI-Stream Interface in Zynq Workflow”.

The examples above use an AMD Zynq target (SoC). You can also do such a prototyping workflow with a pure FPGA Board as these examples show: “Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow”, “Use JTAG AXI Manager to Control HDL Coder Generated IP Core”

You can also find Intel and Microchip examples in our documentation. If your board is not supported, you can even add it. For a SoC board it may be a bit more challenging since you also need a Linux image. We have examples that show this:

• Define Custom Board and Reference Design for Zynq Workflow
• Author a Xilinx Zynq Linux Image for a Custom Zynq Board by Using MathWorks Buildroot
• Define Custom Board and Reference Design for Microchip Pure FPGA Platforms

I hope you find something useful in the provided examples.

Best regards,

Tom

[Julien]

Hello Tom,

For the “Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow” Tutorial, is it necessary to use HDL Coder generated HDL ? Or can you also use a custom-made FPGA design?

Best regards

Julien