How to configure Kria KV260 Vision AI Starter Kit for FPGA-in-the-loop with Simulink?

I would like to use HDL Verifier and the FPGA-in-the-loop with the Kria KV260 board.

In the "fpgaBoardManager" I created a custom board:

The Device Information should be corrected.

For FPGA Input Clock I'm trying to use an external pin such as PMOD but I get the error:

[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.

For this reason I was not able to Validate the board.

For FPGA in the loop I'd like to use JTAG:

To overcome this I tried another way.

I opened the Simulink example project "serial_lpf" and I followed the HDL Workflow Advisor to create FPGA in the loop project. The implementation failed for the same reason as above but it creates the project.

Knowing that the Kria is a System On Module and the clock is generated from MPSoC MultiProcessor, I opened the project with Vivado, I created the following design and I sucessfully generated the bitstream:

So the Simulink circuit receives the PS clock. I checked (using a counter) that the clock is generated as soon as the bit stream is loaded and without configures the PS part.

Simulink generates the co-simulation project and allows me to load bitstream to the FPGA with success. I see the clock (throught the counter) toggling.

But when I press Start for the simulation, I get the following error:

Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.

I'm using Matlab 2023b and Vivado 2023.2.

Is possible to configure a PIN that not fail in FIL Test?

How can I solve the Did not receive version information from the hardware error?

Thanks

[Mohammed]

Hi, Can you share with me the configuration file please?

Mohammed

Answer 1

[Tom Richter]

Hi Fabio,

I suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.com/support/contact_us.html, you can submit a support request and add example or reproduction files. The page also displays phone contact information based on your location.

Best regards,

Tom

[Fabio]

Hi Tom,

I contacted Technical Support as you suggested.

Now I'm trying to change JTAG configuration register and make more investigation and tries.

I will appreciate any ideas you can have

Thanks

Answer 2

[Fabio]

I think that the error "Did not receive version information from the hardware" is related to a wrong communication with the JTAG device and it's independent of loaded bitstream. I get the error both with and without bitstream loaded. I can load bitstream from simulink.

I find these related posts: Same problem on Zynq and Same problem on Virtex.

I checked also FPGA Board Editor.

After further investigation I checked the following things:

• JTAG Chain Position: 1 ---> It is the only value that allow to upload bitstream to FPGA. So I think it's correct.
• Sum of IR length before and after checked with Vivado

So I put IR length before as 0 and IR length after as 4. In previous tries I put 0 and 0 or 4 and 0 but neither works.

• I checked the BSD file for the XCK26_SFVC784 and I set:

USER1          (100100000010)
USER2          (100100000011)
USER3          (100100100010)
USER4          (100100100011)
attribute TAP_SCAN_CLOCK of PS_JTAG_TCK : signal is (30.0e6, BOTH);

For clock I tried 30MHz, 15MHz and 5MHz. Nothing works.

• I compared the configuration with the other UltraScale+ MPSoC and I noticed that are the same IR length before and after, the same USERs, the same frequency. So I tried to copy their configuration:

Nothing works.

Can someone help me? Thanks