- You can use the "Generate HDL Code" button in Simulink Toolstrip:
- Or the "Generate HDL for Subsystem" option from the HDL Coder Block context menu:
- You can also use the "makehdl" command: https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-from-simulink-model-from-command-line.html
- Workflow: "Generic ASIC/FPGA"
- Synthesis tool: "No synthesis tool available on system path" or "No synthesis tool specified"