WLAN LDPC Decoder

Decode LDPC code according to WLAN standard

Since R2021b

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Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The WLAN LDPC Decoder block implements a low-density parity-check (LDPC) decoder using a layered belief propagation with min-sum approximation and normalized min-sum approximation algorithms for decoding LDPC codes according to the wireless local area network (WLAN) standards IEEE^® 802.11n™, 802.11ac™, 802.11ax™, and 802.11ad™. The block accepts log-likelihood ratio (LLR) values, a stream of control signals, a block length, and a code rate as inputs and outputs decoded bits, a stream of control signals, and a signal that indicates when the block is ready to accept new inputs.

The WLAN LPDC Decoder block supports scalar inputs and vector inputs. The block supports early termination to help improve decoding performance and convergence speeds at high signal-noise-ratio (SNR) conditions. For more information about WLAN standards, see [1], [2], and [3].

The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block in the WLAN modem development.

Examples

Decode WLAN LDPC Streaming Data

Simulate WLAN LDPC Decoder block and compare hardware-optimized results with results from Communication Toolbox™ function.

• Open Script

Ports

Input

data — LLR values

scalar | vector

LLR values, specified as a scalar or a vector of size 8-by-1.

For HDL code generation, specify this value in signed fixed point format. The input word length must be in the range from 4 to 16.

Data Types: int8 | int16 | signed fixed point

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the input frame

• end — Indicates the end of the input frame

• valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

blkLenIdx — Block length index

0 | 1 | 2

Block length index, specified as 0, 1, or 2. The block length varies based on the specified block length index.

This table shows the block length index values and their corresponding block lengths.

blkLenIdx Value	Block Length
0	648
1	1296
2	1944

When you specify a value other than 0, 1, or 2, the block discards the frame and sets the nextFrame output port to 1.

Dependencies

To enable this port, set the Standard parameter to IEEE 802.11 n/ac/ax.

Data Types: fixdt(0,2,0)

codeRateIdx — Code rate index

0 | 1 | 2 | 3

Code rate index, specified as 0, 1, 2, or 3. The code rate varies based on the standard and code rate index that you specify.

This table shows the code rate index values and their corresponding code rates based on the standard.

Standard Parameter Value	codeRateIdx Value	Code Rate
IEEE 802.11 n/ac/ax	0	1/2
	1	2/3
	2	3/4
	3	5/6
IEEE 802.11 ad	0	1/2
	1	5/8
	2	3/4
	3	13/16

Data Types: fixdt(0,2,0)

iter — Number of iterations

scalar

Number of iterations, specified as an unsigned integer in the range from 1 to 63.

If you specify an iter value greater than 63 or less than 1, the block overrides your specification and sets the iter value to 8 before decoding.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Max and the Source for number of iterations parameter to Input port.

Data Types: uint8

Output

data — Decoded bits

scalar | vector

Decoded bits, returned as a Boolean scalar or a Boolean vector of size 8-by-1.

For a vector input, if the output data length is not a multiple of 8, the block appends zeros at the end of the output to make it as a multiple of 8.

For example, when you set the Standard parameter to IEEE 802.11 n/ac/ax, the blkLenIdx input port to 0, and the codeRateIdx input port to 2, instead of the block returning the 486 samples, the block appends two zeros to the 486 samples to make it as a multiple of 8. In this case, the block returns 488 samples in 61 (488/8) clock cycles.

Data Types: Boolean

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the output frame

• end — Indicates the end of the output frame

• valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

nextFrame — Block ready indicator

Boolean scalar

Block ready indicator, returned as a Boolean scalar.

The block sets this signal to 1 (true) when the block is ready to accept the start of the next frame. If the block receives an input ctrl.start signal while nextFrame is 0 (false), the block discards the frame in progress and begins processing the new data.

Data Types: Boolean

actIter — Actual number of iterations

scalar

Actual number of iterations the block takes to decode the output, returned as a scalar.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Early.

Data Types: uint8

parityCheck — Parity check status indicator

scalar

Parity check status indicator, returned as a Boolean scalar. The port indicates the status of the parity check after the decoding operation.

• 0 — Indicates that the parity check failed

• 1 — Indicates that the parity check passed

Dependencies

To enable this port, select the Enable parity check output port parameter.

Data Types: Boolean

Parameters

Standard — Type of standard

IEEE 802.11 n/ac/ax (default) | IEEE 802.11 ad

Select the type of standard. For more information, see [1], [2], and [3].

When you set the Standard parameter to IEEE 802.11 ad, the blkLenIdx input port is disabled and the block considers a fixed block length of 672 for its operation.

Algorithm — LDPC decoding algorithm

Min-sum (default) | Normalized min-sum

Select the type of LDPC decoding algorithm. For more information, see Algorithm.

• Min-sum — Use this option to select the layered belief propagation algorithm with a min-sum approximation. For more information, see Min-Sum Approximation.

• Normalized min-sum — Use this option to select the layered belief propagation algorithm with a normalized min-sum approximation. For more information, see Normalized Min-Sum Approximation.

Scaling factor — Scaling factor for normalized min-sum decoding

0.75 (default) | scalar in the range from 0.5 to 1, incremented by 0.0625

Specify the scaling factor as scalar in the range from 0.5 to 1, incremented by 0.0625.

Dependencies

To enable this parameter, set the Algorithm parameter to Normalized min-sum.

Decoding termination criteria — Termination criteria

Max (default) | Early

Select the decoding termination criteria.

• Max — Terminate decoding when the block reaches the number of iterations specified in the block mask or through the iter input port.

• Early — Terminate decoding when the block meets all of the parity checks or when the block reaches the maximum number of iterations provided in the block mask.

Source for number of iterations — Source selection for number of iterations

Property (default) | Input port

Select the source for specifying the number of iterations.

You can set the number of iterations by using either an input port or a parameter.

• Property — Select this option to enable the Number of iterations parameter.

• Input port — Select this option to enable the iter port.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Max.

Number of iterations — Number of decoding iterations

8 (default) | integer in the range from 1 to 63

Specify the number of decoding iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Max and the Source for number of iterations parameter to Property.

Maximum number of iterations — Maximum number of decoding iterations

8 (default) | integer in the range from 1 to 63

Specify the maximum number of decoding iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Early.

Enable parity check output port — Parity check status

off (default) | on

Select this parameter to enable the parityCheck output port to view the status of the parity check.

Algorithms

This figure shows the architecture block diagram of the WLAN LDPC Decoder block. The Controller block controls the layer and iteration count of the decoding process. The Variable node RAM block stores the variable node (VN) messages, and the Check node RAM block stores the check node (CN) messages. The Functional Unit block calculates the VN messages and CN messages based on the layered belief propagation and either the normalized min-sum approximation algorithm or the min-sum approximation algorithm. The Termination/Parity check status block calculates the parity checks and provides the parity check status after each iteration. For more information about decoding algorithms, see the following sections.

Belief Propagation Decoding

The implementation of the belief propagation algorithm is based on the decoding algorithm presented in [4]. For a transmitted LDPC-encoded codeword, c, where $$c=(c_0,c_1,\mathrm{...},c_{n-1})$$, the input to the LDPC decoder is the log-likelihood ratio (LLR) value $$L(c_i)=\log \left(\frac{\mathrm{Pr}(c_i=0|\text{channel output for }{c}_i)}{\mathrm{Pr}(c_i=1|\text{channel output for }{c}_i)}\right)$$.

In each iteration, the key components of the algorithm are updated based on these equations:

$$L(r_{ji})=2\text{atanh}\left({\displaystyle \prod _{i^{\prime }\in V_j\backslash i}\tanh \left(\frac{1}{2}L(q_{i^{\prime }j})\right)}\right)$$,

$$L(q_{ij})=L(c_i)+{\displaystyle \sum _{j^{\prime }\in C_i\backslash j}L(r_{j^{\prime }i})}$$, initialized as $$L(q_{ij})=L(c_i)$$ before the first iteration, and

$$L(Q_i)=L(c_i)+{\displaystyle \sum _{j^{\prime }\in C_i}L(r_{j^{\prime }i})}$$.

At the end of each iteration, $$L(Q_i)$$ is an updated estimate of the LLR value for the transmitted bit $$c_i$$. The value $$L(Q_i)$$ is the soft-decision output for $$c_i$$. If $$L(Q_i)<0$$, the hard-decision output for $$c_i$$ is 1. Otherwise, the output is 0.

Layered Belief Propagation Decoding

The implementation of the layered belief propagation algorithm is based on the decoding algorithm presented in [5], Section II.A. The decoding loop iterates over subsets of rows (layers) of the PCM. For each row, m, in a layer and each bit index, j, the implementation updates the key components of the algorithm based on these equations:

(1) $$L(q_{mj})=L(q_j)-R_{mj}$$,

(2) $$A_{mj}={\displaystyle \sum _{\begin{array}{c}n \in N\left(m\right)\\ n\ne j\end{array}}\text{ψ}(L(q_{mn}))}$$,

(3) $$s_{mj}={\displaystyle \prod _{\begin{array}{c}n \in N\left(m\right)\\ n\ne j\end{array}}\text{sign}(L(q_{mn}))}$$,

(4) $$R_{mj}=-s_{mj}\text{ψ}(A_{mj})$$, and

(5) $$L(q_j)=L(q_{mj})+R_{mj}$$.

For each layer, the decoding equation (5) works on the combined input obtained from the current LLR inputs $$L(q_{mj})$$ and the previous layer updates $$R_{mj}$$.

Because only a subset of the nodes is updated in a layer, the layered belief propagation algorithm is faster compared to the belief propagation algorithm. To achieve the same error rate as attained with belief propagation decoding, use half the number of decoding iterations when using the layered belief propagation algorithm.

Min-Sum Approximation

The implementation of the min-sum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by

$$A_{mj}=\underset{\begin{array}{c}n \in N\left(m\right)\\ n\ne j\end{array}}{\min }(\left|L(q_{mn}) \right|\cdot \alpha )$$,

where α is 1.

Normalized Min-Sum Approximation

The implementation of the normalized min-sum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by

$$A_{mj}=\underset{\begin{array}{c}n \in N\left(m\right)\\ n\ne j\end{array}}{\min }(\left|L(q_{mn}) \right|\cdot \alpha )$$,

where α is in the range (0, 1] and is the scaling factor specified by the Scaling factor parameter. This equation is an adaptation of equation (4) presented in [6].

Latency

The latency of the block varies based on the selected Standard parameter, the values of the blkLenIdx and codeRateIdx input ports, and the number of iterations. Because the latency varies, use the nextFrame control signal output port to determine when the block is ready for a new input frame.

Scalar Input

The latency of the block is equal to r x (t + m x 9) + d. In this calculation, r is the number of iterations, t is twice the total number of non –1 elements in the PCM, m is the number of rows in the PCM, and d is the pipeline delays. For scalar inputs, d is 13.

This figure shows a sample output and latency of the WLAN LDPC Decoder block for a scalar input when you set the Standard parameter to IEEE 802.11 n/ac/ax, the Algorithm parameter to Min-sum, the Number of iterations parameter to 8 and the blkLenIdx and the codeRateIdx input port values both to 0 and 0. The latency of the block is 2933 clock cycles.

Vector Input

The latency of the block is equal to r x (t + m x 9) + d. In this calculation, r is number of iterations, t is twice the total number of non –1 elements in the PCM, m is the number of rows in the parity check matrix, and d is the pipeline delays. For vector inputs, when you set the Standard parameter to:

• IEEE 802.11 n/ac/ax, d is 35, 32, and 35 for blkLenIdx input port values 0, 1, and 2, respectively

• IEEE 802.11 ad, d is 26

This figure shows a sample output and latency of the WLAN LDPC Decoder block for a vector input when you set the Standard parameter to IEEE 802.11 ad, the Algorithm parameter to Normalized min-sum, the Number of iterations parameter to 8, and the codeRateIdx input port value to 0. The latency of the block is 1518 clock cycles.

SNR and BER Plots

This section shows the SNR and BER plots of the block for specified inputs and parameter settings.

This plot shows the performance of the block for a 4 bit QPSK-modulated LLR input, when you set the Standard parameter to IEEE 802.11 n/ac/ax, the Algorithm parameter to Min-sum, the blkLenIdx input port value to 0 (block length of 648) and the codeRateIdx input port value to 0, 1, 2, and 3 (code rates of 1/2, 2/3, 3/4, and 5/6, respectively).

This plot shows the performance of the block for a 4 bit QPSK-modulated LLR input, when you set the Standard parameter to IEEE 802.11 ad, the Algorithm parameter to Normalized min-sum, and the codeRateIdx input port value to 0, 1, 2, and 3 (code rates of 1/2, 5/8, 3/4, and 13/16, respectively). In this case, the block length is fixed to 672.

Performance

The performance of the synthesized HDL code varies with the target and synthesis options. It also varies based on the type of algorithm, decoding termination criteria, and the word length of the input LLR values.

This table shows the resource and performance data synthesis results of the block for the supported WLAN standards when you set the Algorithm parameter to Min-sum, the Number of iterations parameter to 8, and the input LLR values as data type fixdt(1,4,0). The generated HDL is targeted to the AMD^® Zynq^® UltraScale+™ MPSoC - ZCU102 Evaluation Board.

Standard	Input Data	Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
IEEE 802.11 n/ac/ax	Scalar	16837	13924	0.5	435.4
	Vector	21365	17131	0.5	400.2
IEEE 802.11 ad	Scalar	6487	6209	0.5	464.7
	Vector	8844	7294	1	458.7

References

[1] IEEE Std 802.11™-2016 (Revision of IEEE Std 802.11-2012). “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications.” IEEE Standard for Information technology — Telecommunications and information exchange between systems. Local and metropolitan area networks — Specific requirements.

[2] IEEE STD 802.11ad-2012 (Amendment to IEEE Std 802.11-2012, as amended by IEEE Std 802.11ae™-2012 and IEEE Std 802.11a™-2012). “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications. Amendment 4: Enhancements for Very High Throughput Operation in Bands below 6 GHz.” IEEE Standard for Information technology — Telecommunications and information exchange between systems. Local and metropolitan area networks — Specific requirements.

[3] IEEE Std 802.11ah™-2016 (Amendment to IEEE Std 802.11-2016 as amended by IEEE Std 802.11ai™-2016). “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications. Amendment 2: Sub 1 GHz License Exempt Operation.” IEEE Standard for Information technology — Telecommunications and information exchange between systems. Local and metropolitan area networks — Specific requirements.

[4] Gallager, R. “Low-Density Parity-Check Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. https://doi.org/10.1109/TIT.1962.1057683.

[5] Hocevar, D.E. “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes.” In IEEE Workshop OnSignal Processing Systems, 2004. SIPS 2004., 107–12. Austin, Texas, USA: IEEE, 2004. https://doi.org/10.1109/SIPS.2004.1363033.

[6] Chen, Jinghu, R.M. Tanner, C. Jones, and Yan Li. "Improved min-sum decoding algorithms for irregular LDPC codes." In Proceedings. International Symposium on Information Theory, 2005. ISIT 2005. https://doi: 10.1109/ISIT.2005.1523374.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2021b