Image Statistics

Calculate mean, variance, and standard deviation

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Libraries:
Vision HDL Toolbox / Statistics

Description

The Image Statistics block calculates the mean, variance, and standard deviation of streaming video data. Each calculation is performed over all pixels in the input region of interest (ROI). The block implements the calculations by using hardware-efficient algorithms.

Ports

This block uses a streaming pixel interface with a bus for frame control signals. This interface enables the block to operate independently of image size and format. The pixel input port supports single pixel streaming or multipixel streaming. Single pixel streaming accepts a single pixel value each clock cycle. Multipixel streaming accepts a vector of M pixels per clock cycle to support high-frame-rate or high-resolution formats. The M value corresponds to the Number of pixels parameter of the Frame To Pixels block. Along with the pixel, the block accepts a pixelcontrol bus that contains five control signals. The control signals indicate the validity of each pixel and their location in the frame. For multipixel streaming, one set of control signals applies to all pixels in the vector. To convert a frame (pixel matrix) into a serial pixel stream and control signals, use the Frame To Pixels block. For a full description of the interface, see Streaming Pixel Interface.

Input

pixel — Input pixel stream

scalar | vector

For single pixel streaming, specify pixel as an unsigned scalar value that represents grayscale intensity. For multipixel streaming, specify pixel as a column vector of Number of pixels pixel intensity values. Number of pixels can be two, four, or eight.

The software supports double and single data types for simulation, but not for HDL code generation.

Data Types: uint8 | uint16 | fixdt(0,W,0) | double | single

ctrl — Control signals associated with pixel stream

pixelcontrol bus

The pixelcontrol bus contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

For multipixel streaming, each vector of pixel values has one set of control signals. Because the vector has only one valid signal, the pixels in the vector must be either all valid or all invalid. The hStart and vStart signals apply to the pixel with the lowest index in the vector. The hEnd and vEnd signals apply to the pixel with the highest index in the vector.

Data Types: bus

Output

The block uses full-precision arithmetic for internal calculation. At the output ports, intermediate data is cast back to the input type by using the following fixed-point settings: Rounding method = Nearest, and Overflow action = Saturate. The table shows the output word length for each calculation, relative to the input word length (IWL).

Mean	Variance	Std. Deviation
IWL	2×IWL	2×IWL

mean — Mean of most recent input frame completed

scalar

Mean of the most recent input frame completed, returned as a scalar. The data type of mean is same as the data type of pixel.

Data Types: uint8 | uint16 | fixdt(0,W,0) | double | single

var — Variance of most recent input frame completed

scalar

Variance of the most recent input frame completed, returned as a scalar. The data type of var is same as the data type of pixel.

Data Types: uint8 | uint16 | fixdt(0,W,0) | double | single

stdDev — Standard deviation of most recent input frame completed

scalar

Standard deviation of the most recent input frame completed, returned as a scalar. The data type of stdDev is same as the data type of pixel.

Data Types: uint8 | uint16 | fixdt(0,W,0) | double | single

validOut — Computations completed

boolean

The block sets this output to true when the statistic outputs for a frame are ready.

Data Types: Boolean

Parameters

Enable mean output — Calculate the mean of each input frame

on (default) | off

Select this parameter to enable the mean port and calculate the mean of each input frame.

Enable variance output — Calculate the variance of each input frame

on (default) | off

Select this parameter to enable the var port and calculate the variance of each input frame.

Enable std. deviation — Calculate the standard deviation of each input frame

on (default) | off

Select this parameter to enable the stdDev port and calculate the standard deviation of each input frame.

Tips

• To change the size and dimensions of the ROI, you can manipulate the input video stream control signals. See Regions of Interest.

• The number of valid pixels in the input image affects the accuracy of the mean approximation. To avoid approximation error, use an image that contains a multiple of 64ⁿ pixels, up to 64ⁿ⁺¹ pixels, where n equals 0, 1, 2, or 3. For details of the mean approximation, see Algorithm.

• The block calculates statistics over frames up to 64⁴ (16, 777, 216) pixels in size. This size supports HD frames.

Algorithms

Architecture

The calculations of mean, variance, and standard deviation build off each other. For hardware efficiency, the calculation logic is shared as shown.

For multipixel input, the block implements an extra accumulator stage at the beginning of the calculations.

Mean

The equation to calculate the precise mean pixel value requires large internal word lengths and expensive division logic.

$$\mu =\frac{1}{M\ast N}{\displaystyle \sum _{i=1}^M{\displaystyle \sum _{j=1}^N{x}_{ij}}}$$

Instead of using this equation, the block calculates the mean by a series of four accumulators that compute the mean of a segment of pixels. First, the block finds the sum of a window of 64 pixels, and normalizes.

$${\mu }_{L_1}=\frac{1}{64}{\displaystyle \sum _{n=1}^{64}{x}_n}$$

Then it accumulates 64 of the previous windows, and normalizes.

$${\mu }_{L_2}=\frac{1}{64}{\displaystyle \sum _{n=1}^{64}{\mu }_{n{L}_1}}$$

A third accumulator sums 64 of the 64×64 windows, and normalizes the same way.

$${\mu }_{L_3}=\frac{1}{64}{\displaystyle \sum _{n=1}^{64}{\mu }_{n{L}_2}}$$

The fourth accumulator sums 64 of the 64×64×64 windows and normalizes.

$${\mu }_{L_4}=\frac{1}{64}{\displaystyle \sum _{n=1}^{64}{\mu }_{n{L}_3}}$$

Each valid pixel is accumulated as it arrives. Its location within a line or frame does not affect the accumulation logic.

When vEnd is received, the block promotes any remaining data in the four levels of mean calculation to calculate the final output. If an accumulator counter is not at 64 when vEnd arrives, that level normalizes by the actual value of the counter. The constants for this multiplication are stored in a lookup table (LUT). The four accumulators share a single LUT and multiplier. The values in the LUT are in ufix18_en17 data type so that the multiplier fits into a DSP block on an FPGA.

This method of mean calculation is accurate when the number of pixels in the frame aligns vEnd with the final accumulator rollover. This alignment occurs at level 2 when the frame contains a multiple of 64 pixels, and fewer than 64²(4096) pixels. It occurs at level 3 when the frame contains a multiple of 4096 pixels. It occurs at level 4 when the frame contains a multiple of 64³ pixels. This method is also accurate when the frame has fewer than 64 pixels, because only the first accumulator is needed.

However, when the number of pixels in the frame does not fit these conditions, the block must normalize the final accumulation before the counter reaches 64. This normalization introduces an error in the calculation at subsequent levels. The figure shows the normalization error introduced in the mean calculation by image sizes under 4096 pixels. The spikes occur where an image size is just over a multiple of 64 pixels.

For images larger than 4096 pixels, the same effect occurs at multiples of 4096 pixels, and at multiples of 64³ pixels.

Variance

The block calculates the variance of the input pixels by using this equation:

$${\sigma }^2=(\frac{1}{M*N}{\displaystyle \sum _{i=1}^M{\displaystyle \sum _{j=1}^N{x}_{ij}^2}})-{\mu }^2$$

The mean and the mean of the squared input are calculated in parallel. The block calculates the mean of squares using the same approximation method used to calculate the mean, as described in the previous section.

Standard Deviation

The block calculates the square root of the variance by using a pipelined bit-set-and-check algorithm. This algorithm computes the square root by using addition and shifts, rather than multipliers. For an N-bit input, the result has N bits of accuracy.

This method is hardware efficient for general inputs. If your data has known characteristics that allow for a more efficient square root implementation, you can disable the calculation in this block and construct your own logic from HDL-supported blocks.

Regions of Interest

Statistics are often calculated on small regions of interest (ROI) rather than an entire video frame. This block performs calculations on all valid pixels between the vStart and vEnd signals in the ctrl bus and does not track pixel location within the frame. You can use the ROI Selector block to select a smaller region of the frame before passing the video stream to this block. For an example that selects multiple small ROIs from a larger image and compares the statistics of each region, see Multi-Zone Metering.

The Image Statistics block calculates statistics over frames up to 64⁴ (16,777,216) pixels in size. If you provide an image with more than 64⁴ pixels, the block calculates the requested statistics on only the first 16,777,216 pixels and then asserts validOut. The block ignores extra pixels until it receives a vEnd signal.

Latency

The latency from vEnd to validOut depends on the calculations you select.

When the block receives a vEnd signal that is true, it combines the remaining data in the four levels of mean calculation to calculate the final output. This final step takes four cycles per level, resulting in a maximum of 16 cycles of latency between the input vEnd signal and the validOut signal. Once the mean is available, the variance calculation takes four cycles. The square root logic requires input word length (IWL) cycles of latency.

If a calculation is not selected, and is not needed for other selected calculations, that logic is excluded from the generated HDL code.

The table shows the calculation logic and latency for various block configurations.

Mean	Variance	Std. Deviation	Logic Excluded From HDL	Latency (cycles)
✓	✓	✓		[4n]+4+IWL, (where n is the number of accumulator levels required for the input size)
✓			variance and square root	[4n]
	✓		square root	[4n]+4
		✓		[4n]+4+IWL
✓	✓		square root	[4n]+4
✓		✓		[4n]+4+IWL
	✓	✓		[4n]+4+IWL

Note

You must have a vertical blanking interval of at least 16 cycles between the vEnd of one input frame and the vStart of the next input frame. This period lets the block finish processing the current frame before the new one arrives. For more information, see Configure Blanking Intervals.

Performance

This table shows the resource use after synthesis of the block for the Xilinx^® Zynq^®-7000 SoC ZC706 Evaluation Kit with single-pixel uint8 input and the default parameter settings. The design achieves a clock frequency of 246 MHz.

Resource	Usage
Slice LUTs	825
Slice Registers	966
DSP48	5
Block RAM	0.5

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2015a

R2023b: Multipixel streaming

The Image Statistics block now supports multipixel streams. For multipixel streaming, the block supports input column vectors of 2, 4, or 8 pixels. The ctrl port remains scalar, and the control signals in the pixelcontrol bus apply to all pixels in the vector. The output ports that represent the statistics of the image remain scalar.