Model Configuration Parameters for Texas Instruments F29x (C29x)

R2026b

The F29x family (F29H85x) uses the C29x CPU architecture, which introduces UART peripherals (replacing SCI), RTDMA (replacing DMA), and ePWM X-BAR. To configure hardware parameters for F29x processors:

1. In the Simulink^® Editor, select Modeling > Model Settings.

2. In the Configuration Parameter dialog box, click Hardware Implementation.

3. Set the Hardware board parameter to TI F29x Based or TI F29H85x LaunchPad.

4. Select the processing unit (c29xCPU1, c29xCPU2, or c29xCPU3).

5. Click Apply.

For peripherals shared with C28x-based processors (ADC, DAC, CMPSS, ePWM, eCAP, eQEP, I2C, SPI, MCAN, SDFM, CLB, Input X-BAR, Output X-BAR, CLB X-BAR, GPIO, Watchdog, and External Interrupt), the parameter structure is similar to the main Model Configuration Parameters for Texas Instruments C2000 Processors section. This section documents the peripherals and settings that are unique to the C29x architecture.

Hardware Board Settings

For each hardware board you select, you can configure the board parameters according to your requirements.

Build Options

Parameter	Description	Default Value
Build action	Define how Embedded Coder® responds when you build your model.	Build, load and run
Device Name	Select the target device series within the F29x family.
Boot from flash (stand-alone execution)	Store the generated executable in on-chip flash memory so the application runs after a power cycle without a debugger connection.	Selected
Enable TMU	Enable the Trigonometric Math Unit for hardware-accelerated trigonometric operations in generated code.	Selected
Disable parallel build	Disable parallel compilation during the build process.	Not selected
Use custom linker command file	Specify a custom linker command file instead of the auto-generated one.	Not selected
CCS hardware configuration file	Path to the Code Composer Studio target configuration file (.ccxml) for the debug probe connection.	$(TI_C2000_DIR)/CCS_Config/f29h850TU9.ccxml

Clocking

Parameter	Description	Default Value
Desired CPU Clock in MHz	Target CPU clock frequency. The PLL settings are computed to achieve this frequency from the selected clock source.	200
CPU clock source	Select the oscillator source for the system PLL. Options: Internal oscillator (INTOSC1), Internal oscillator (INTOSC2), External oscillator (XTAL), Single-ended external oscillator (XTAL_SE).	Internal oscillator (INTOSC2)
Oscillator clock (OSCCLK) frequency in MHz	Frequency of the selected oscillator clock input to the PLL.	10
Auto set PLL based on OSCCLK and CPU clock	Automatically calculate PLL multiplier and divider values to achieve the desired CPU clock from the oscillator frequency.	Selected
System PLL reference divider (SYSPLLMULT_REFDIV)	PLL input reference divider. Valid range: 1–32.	1
System PLL multiplier (SYSPLLMULT_IMULT)	PLL integer multiplier. Valid range: 1–127.	40
PLL output divider (SYSPLLMULT_ODIV)	PLL output divider. Valid range: 1–32.	1
System clock divider (SYSDIVSEL)	Divider applied to the PLL output to produce SYSCLKOUT. PLLSYSCLK = PLLRAWCLK / SYSDIVSEL.	2

UART_x

Parameter	Description	Default Value
Enable UART Loopback	Enable internal loopback from Tx to Rx buffer for self-test and diagnostics.	Not selected
Desired baud rate in bits/sec	Specify the desired baud rate for data transmission.	115200
Closest Achievable Baud rate (in bits/sec)	Calculated baud rate based on the desired baud rate and the system clock frequency. This value is read-only.
Number of stop bits	Number of stop bits to indicate the end of a data frame. Options: 1, 2.	1
Parity mode	Parity mode for error detection. Options: None, Odd, Even, One, Zero.	None
Pin assignment(Tx)	Select a GPIO pin for UART data transmission. Available pins vary by UART module.	GPIO42 (UART_A)
Pin assignment(Rx)	Select a GPIO pin for UART data reception. Available pins vary by UART module.	GPIO43 (UART_A)
Enable Transmit Interrupt	Trigger a UART transmit interrupt when data is copied to the transmit FIFO.	Not selected
Enable Receive Interrupt	Enable the UART receive interrupt for incoming data. This parameter is enabled by default for DMA configuration after data receive.	Selected

The F29x family provides six UART modules (UART_A through UART_F). Each module has independent pin assignment and configuration. UART replaces the SCI peripheral used on C28x-based processors.

RTDMA

Parameter	Description	Default Value
Priority mode	Select the channel arbitration mode. Options: Round-robin, Software.	Round-robin
Enable RTDMA channel	Enable a specific RTDMA channel for configuration. Each RTDMA module provides 4 channels.	Not selected
Data size	Size of data transferred per burst element. Options: 8 bit, 16 bit, 32 bit, 64 bit.	8 bit
Interrupt source	Select the peripheral interrupt event that triggers a DMA burst for the channel.	None
Burst size	Number of data words in a single burst transfer. Valid range: 1–32.	1
Transfer size	Number of bursts in one complete transfer. Valid range: 1–65536.	1
Source begin address	Starting address for the source address pointer.	0x10000
Destination begin address	Starting address for the destination address pointer.	0x12000
Source burst step	Address increment applied to the source pointer after each word in a burst. Valid range: −4096 to 4095.	0
Destination burst step	Address increment applied to the destination pointer after each word in a burst. Valid range: −4096 to 4095.	0
Source transfer step	Address increment applied to the source pointer after each burst. Valid range: −4096 to 4095.	0
Destination transfer step	Address increment applied to the destination pointer after each burst. Valid range: −4096 to 4095.	0
Source wrap size	Number of bursts before returning the source address pointer to the begin address. Valid range: 1–65536.	65536
Destination wrap size	Number of bursts before returning the destination address pointer to the begin address. Valid range: 1–65536.	65536
Source wrap step	Address increment applied to the source pointer at wrap. Valid range: −4096 to 4095.	0
Destination wrap step	Address increment applied to the destination pointer at wrap. Valid range: −4096 to 4095.	0
Set channel software priority	Software-defined priority for this channel when priority mode is set to Software. 0 is highest priority.	1
Enable first DMA event to trigger the full transfer (one shot mode)	Complete the entire transfer (all bursts) on a single trigger event.	Not selected
Do not disable the DMA channel after the transfer is complete (continuous mode)	Keep the channel active after transfer completion so it can respond to subsequent trigger events without re-enabling.	Selected
Generate interrupt	Generate an interrupt at a specified point in the transfer. Options: Never, At beginning of new transfer, At end of transfer.	Never
Enable overflow interrupt	Generate an interrupt when an overflow condition occurs.	Not selected

The F29x family provides two RTDMA modules (RTDMA1 and RTDMA2), each with 4 channels. RTDMA replaces the DMA peripheral used on C28x-based processors and supports 8, 16, 32, and 64-bit data transfers.

ePWM X-BAR

Parameter	Description	Default Value
Select trip	Select the ePWM X-BAR trip signal to configure (TRIP1 through TRIP16), or Disable all.	Disable all
Select trip input signals	Select the input signal routed to the selected trip output.	None
Invert TRIPx output	Invert the polarity of the selected trip output signal.	Not selected

The ePWM X-BAR routes external and internal signals to ePWM trip inputs (TRIP1 through TRIP16) for fault protection. This crossbar is specific to the C29x architecture and is separate from the Input X-BAR and Output X-BAR.

PIL

Parameter	Description	Default Value
Communication interface	Communication interface for processor-in-the-loop testing.	serial
UART module	Select the UART module for PIL communication. Options: UART_A through UART_F.	UART_A
Serial port in MATLAB preferences	Select the host serial port for PIL communication.

External Mode

Parameter	Description	Default Value
UART module	Select the UART module for serial External Mode communication.	UART_A
Serial port in MATLAB preferences	Select the host serial port for External Mode communication.
CAN module	Select the MCAN module for CAN-based External Mode. Options: MCAN_A through MCAN_F.	MCAN_A
Rx read source	Select the receive FIFO for CAN External Mode. Options: FIFO0, FIFO1.	FIFO0
Use a dedicated timer to improve time stamp accuracy	Allocate a hardware timer for accurate time stamp logging during External Mode monitoring.	Not selected

Overrun Detection

Parameter	Description	Default Value
Enable overrun detection	Enable overrun detection to identify when a base rate task does not complete before the next trigger.	Not selected
Set/Clear/Toggle GPIO	Use a GPIO pin to signal an overrun condition.	Selected
Digital output pin to set on overrun	GPIO pin number to assert when an overrun is detected.	34
Set GPIO mode	Action to perform on the GPIO pin during overrun. Options: Set, Clear, Toggle.	Set
Additional notification option	Additional action on overrun. Options: None, Trigger interrupt, Call user-defined function.	None