# CMOS NAND

Behavioral model of CMOS NAND gate

**Libraries:**

Simscape /
Electrical /
Integrated Circuits /
Logic

## Description

The CMOS NAND block represents a CMOS NAND logic gate behaviorally:

The block output logic level is

`HIGH`

if the logic levels of both of the gate inputs are 0.The block output logic level is

`LOW`

otherwise.

The block determines the logic levels of the gate inputs as follows:

If the gate voltage is greater than the threshold voltage, the block interprets the input as logic 1.

Otherwise, the block interprets the input as logic 0.

The *threshold voltage* is the voltage value at midpoint between
the **High level input voltage** parameter value and the **Low
level input voltage** parameter value.

**Note**

To improve simulation speed, the block does not model all the internal individual MOSFET devices that make up the gate. See Assumptions and Limitations for details.

The block models the gate as follows:

The gate inputs have infinite resistance and finite or zero capacitance.

The gate output offers a selection of two models:

`Linear`

and`Quadratic`

. For more information, see Selecting the Output Model for Logic Blocks. Use the**Output current-voltage relationship**parameter to specify the output model.You can specify propagation delay for both output models. For

`Linear`

output, the block sets the value of the gate output capacitor such that the resistor-capacitor time constant equals the**Propagation delay**parameter value. For`Quadratic`

output, the gate input demand is lagged to approximate the**Propagation delay**parameter value.

The block initial conditions depend on the output model selected:

For

`Linear`

model, the high initial condition corresponds to the**High level output voltage**parameter value,`V_OH`

, and the low initial condition corresponds to the**Low level output voltage**parameter value,`V_OL`

.For

`Quadratic`

model, the high initial condition is a value close to the**Supply voltage**parameter value,`Vcc`

, and the low initial condition is close to`0`

.

The block output voltage depends on the output model selected:

For

`Linear`

model, output high is the**High level output voltage**parameter value, and output low is the**Low level output voltage**parameter value.For

`Quadratic`

model, the output voltage for High and Low states is a function of the output current, as explained in Quadratic Model Output and Parameters. For zero load current, output high is Vcc (the**Supply voltage**parameter value), and output low is zero volts.

### Voltage Plot

To access a voltage plot for each electrical port, in your model, right-click the block and,
from the context menu, select **Electrical** > **Basic Characteristics**.

## Examples

## Assumptions and Limitations

The block does not model the internal individual MOSFET devices that make up the gate
(except for the final MOSFET pair if you select the `Quadratic`

option for the **Output current-voltage relationship** parameter). This
limitation has the following implications:

The block does not accurately model the gate's response to input noise and inputs that are around the logic threshold voltage.

The block does not accurately model dynamic response.

Circuits that involve a feedback path around a set of logic gates may require a nonzero propagation delay to be set on one or more gates.

## Ports

### Conserving

## Parameters

## Extended Capabilities

## Version History

**Introduced in R2008b**

## See Also

CMOS AND | CMOS Buffer | CMOS NOR | CMOS NOT | CMOS OR | CMOS XOR | Schmitt Trigger | S-R Latch